ST STM32L4+ Series Reference Manual page 577

RM0432
The data length register (OCTOSPI_DLR) has no meaning in Memory-mapped mode.
When the OCTOSPI is used in Memory-mapped mode, the frames are constructed in the
following way:
1. Specify the frame timing in OCTOSPI_TCR for read operation.
2. Specify the frame format in OCTOSPI_CCR for read operation.
3. Specify the instruction in OCTOSPI_IR.
4. Specify the optional alternate byte to be sent right after the address phase in
OCTOSPI_ABR for read operation.
5. Specify the frame timing in OCTOSPI_WTCR for write operation.
6. Specify the frame format in OCTOSPI_WCCR for write operation.
7. Specify the instruction in OCTOSPI_WIR.
8. Specify the optional alternate byte to be sent right after the address phase in
OCTOSPI_WABR for read operation.
All the configuration operations must be completed before the first access to the memory
area. On the first access, the OCTOSPI becomes busy, and no further configuration is
allowed.
OCTOSPI delayed data sampling when no DQS is used
By default, when no DQS is used, the OCTOSPI samples the data driven by the external
device one half of a CLK cycle after the external device drives the signal.
In case of any external signal delays, it may be useful to sample the data later. Using the
SSHIFT bit in OCTOSPI_TCR, the sampling of the data can be shifted by half of a CLK
cycle.
The firmware must clear SSHIFT when the data phase is configured in DTR mode
(DDTR = 1).
OCTOSPI delayed data sampling when DQS is used
When external DQS is used as a sampling clock, it can be shifted in time to compensate the
data propagation delay. This shift is performed by an external delay block
the OCTOSPI. The control of this feature depends on the device implementation (see the
product reference manual for more
In certain configuration cases, this external delay block is implemented but is not useful, so
it can be bypassed by setting DLYBYP bit in OCTOSPI_DCR1.
Sending the instruction only once (SIOO)
A Flash memory can provide a mode where an instruction must be sent only with the first
command sequence, while subsequent commands start directly with the address. The user
can take advantage of this type of features using the SIOO bit in OCTOSPI_CCR.
The SIOO is valid for Memory-mapped mode only. If this bit is set, the instruction is sent only
for the first command following a write to OCTOSPI_CCR.
Subsequent command sequences skip the instruction phase, until there is a write to
OCTOSPI_CCR. The SIOO has no effect when IMODE[1:0] = 00 (no instruction).
SIOO mode is not supported when any of the communication regulation, CS boundary or
refresh features are used.
details).
RM0432 Rev 6
Octo-SPI interface (OCTOSPI)
located outside
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