ST STM32L4+ Series Reference Manual page 839

RM0432
decoding. There are two possible settings of Manchester codings (see SITP[1:0] bits in
DFSDM_CHyCFGR1 register):
•
signal rising edge = log 0; signal falling edge = log 1
•
signal rising edge = log 1; signal falling edge = log 0
The recovered clock signal frequency for Manchester coding must be in the range
0 - 10 MHz and less than f
To correctly receive Manchester coded data, the CKOUTDIV divider (in
DFSDM_CH0CFGR1 register) must be set with respect to expected Manchester data rate
according formula:
DFSDMCLK
( ( ) T ×
CKOUTDIV + 1
SYSCLK
Digital filter for sigma delta modulators (DFSDM)
/6.
) T < <
Manchester clock
RM0432 Rev 6
( × ×
2 CKOUTDIV T
SYSCLK
)
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