ST STM32L4+ Series Reference Manual page 422

Chrom-ART Accelerator controller (DMA2D)
•
Manual loading
The application has to program the CLUT manually through the DMA2D AHB slave
port to which the local CLUT memory is mapped.The foreground CLUT is located at
address offset 0x0400 and the background CLUT at address offset 0x0800.
The CLUT format is 24 or 32 bits. It is configured through the CCM bit of the
DMA2D_FGPFCCR register (foreground CLUT) or DMA2D_BGPFCCR register
(background CLUT) as shown in
The way the CLUT data are organized in the system memory is specified in
data order in system
CLUT Color Mode
ARGB8888
RGB888
13.3.6 DMA2D blender
The DMA2D blender blends the source pixels by pair to compute the resulting pixel.
The blending is performed according to the following equation:
No configuration register is required by the blender. The blender usage depends on the
DMA2D operating mode defined in MODE[2:0] field of the DMA2D_CR register.
422/2301
occurs, a CLUT access error interrupt is raised assuming
DMA2D_CR.
Table 66. Supported CLUT color mode
CCM
0
1
memory.
Table 67. CLUT data order in system memory
@ + 3
A [7:0]
0
B [7:0]
1
G [7:0]
2
R [7:0]
3
with α
C =
OUT
Table 66: Supported CLUT color
@ + 2
R [7:0]
0
R [7:0]
0
B [7:0]
2
G [7:0]
3
α . α
FG BG
=
Mult
255
α = α + α - α
OUT FG BG
C .α + C .α - C
FG FG BG BG
α
OUT
Division is rounded to the nearest lower integer
RM0432 Rev 6
CAEIE is set to '1' in
mode.
CLUT color mode
32-bit ARGB8888
24-bit RGB888
@ + 1
G [7:0]
0
G [7:0]
0
R [7:0]
1
B [7:0]
3
Mult
.α
BG Mult
with C = R or G or B
RM0432
Table 67: CLUT
@ + 0
B [7:0]
0
B [7:0]
0
G [7:0]
1
R [7:0]
2