ST STM32L4+ Series Reference Manual page 196

Power control (PWR)
Stop 2 mode with SRAM3 retention when the RRSTP bit is set in PWR_CR1 register.
Stop 1 offers the largest number of active peripherals and wakeup sources, a smaller
wakeup time but a higher consumption than Stop 2. In Stop 0 mode, the main regulator
remains ON, which allows the fastest wakeup time but with much higher consumption.
The active peripherals and wakeup sources are the same as in Stop 1 mode.
The system clock, when exiting from Stop 0, Stop 1 or Stop 2 mode, can be either MSI
up to 48 MHz or HSI16, depending on the software configuration.
Refer to
•
Standby mode: V
SRAM2 contents:
–
–
–
–
All clocks in the V
are disabled. The LSI and the LSE can be kept running.
The RTC can remain active (Standby mode with RTC, Standby mode without RTC).
The system clock, when exiting Standby modes, is MSI from 1 MHz up to 8 MHz.
Refer to
•
Shutdown mode: V
stopped, the PLL, the MSI, the HSI16, the LSI and the HSE are disabled. The LSE can
be kept running. The system clock, when exiting the Shutdown mode, is MSI at 4 MHz.
In this mode, the supply voltage monitoring is disabled and the product behavior is not
guaranteed in case of a power voltage drop. Refer to
In addition, the power consumption in Run mode can be reduced by one of the following
means:
•
Slowing down the system clocks
•
Gating the clocks to the APB and AHB peripherals when they are unused.
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PWR_CR1 register (default setting).
Section 5.3.6: Stop 0 mode
domain is powered off. However, it is possible to preserve the
CORE
For STM32L4Rxxx and STM32L4Sxxx devices:
Standby mode with SRAM2 retention when the bit RRS is set in PWR_CR3
register. In this case, SRAM2 is supplied by the low-power regulator.
Standby mode when the bit RRS is cleared in PWR_CR3 register. In this case the
main regulator and the low-power regulator are powered off.
For STM32L4P5xx and STM32L4Q5xx devices:
Standby mode with full or only the upper 4 Kbytes of SRAM2 retention when the
RRS[1:0] bits are set to '01' or '10' respectively in the PWR_CR3 register. In this
case, the SRAM2 is supplied by the low-power regulator.
Standby mode when the RRS[1:0] bits are cleared in PWR_CR3 register. In this
case the main regulator and the low-power regulator are powered off.
domain are stopped, the PLL, the MSI, the HSI16 and the HSE
CORE
Section 5.3.9: Standby
domain is powered off. All clocks in the V
CORE
and Section 5.3.8: Stop 2
mode.
RM0432 Rev 6
mode.
domain are
CORE
Section 5.3.10: Shutdown
RM0432
mode.