ST STM32L4+ Series Reference Manual page 512

Flexible static memory controller (FSMC)
Bit number
31:30
29:28
27:24
23:20
19:16
15:8
7:4
3:0
Mode 2/B - NOR Flash
A[25:0]
NADV
NEx
NOE
NWE
D[15:0]
512/2301
Table 97. FMC_BWTRx bitfields (mode A)
Bit name
Duration of the data hold phase (DATAHLD+1 HCLK cycles for write
DATAHLD
accesses).
ACCMOD 0x0
DATLAT Don't care
CLKDIV Don't care
BUSTURN Time between NEx high to NEx low (BUSTURN HCLK).
Duration of the second access phase (DATAST HCLK cycles) for write
DATAST
accesses.
ADDHLD Don't care
Duration of the first access phase (ADDSET HCLK cycles) for write
accesses.
ADDSET
Minimum value for ADDSET is 0.
Figure 52. Mode 2 and mode B read access waveforms
High
ADDSET HCLK cycles
RM0432 Rev 6
Value to set
Memory transaction
Data driven by memory
DATAST HCLK cycles
RM0432
DATAHLD
HCLK cycles
MSv41678V1