ST STM32L4+ Series Reference Manual page 435

RM0432
13.5.3 DMA2D interrupt flag clear register (DMA2D_IFCR)
Address offset: 0x0008
Reset value: 0x0000 0000
31 30 29
Res. Res. Res. Res.
15 14 13
Res. Res. Res. Res.
Bits 31:6 Reserved, must be kept at reset value.
Bit 5 CCEIF: Clear configuration error interrupt flag
Bit 4 CCTCIF: Clear CLUT transfer complete interrupt flag
Bit 3 CAECIF: Clear CLUT access error interrupt flag
Bit 2 CTWIF: Clear transfer watermark interrupt flag
Bit 1 CTCIF: Clear transfer complete interrupt flag
Bit 0 CTEIF: Clear Transfer error interrupt flag
13.5.4 DMA2D foreground memory address register (DMA2D_FGMAR)
Address offset: 0x000C
Reset value: 0x0000 0000
31 30 29
rw rw rw
15 14 13
rw rw rw
Bits 31:0 MA[31:0]: Memory address
28 27 26 25
Res. Res. Res.
12 11 10 9
Res. Res. Res.
Programming this bit to 1 clears the CEIF flag in the DMA2D_ISR register
Programming this bit to 1 clears the CTCIF flag in the DMA2D_ISR register
Programming this bit to 1 clears the CAEIF flag in the DMA2D_ISR register
Programming this bit to 1 clears the TWIF flag in the DMA2D_ISR register
Programming this bit to 1 clears the TCIF flag in the DMA2D_ISR register
Programming this bit to 1 clears the TEIF flag in the DMA2D_ISR register
28 27 26 25
rw rw rw rw
12 11 10 9
rw rw rw rw
Address of the data used for the foreground image. This register can only be written
when data transfers are disabled. Once the data transfer has started, this register is
read-only.
The address alignment must match the image format selected e.g. a 32-bit per pixel
format must be 32-bit aligned, a 16-bit per pixel format must be 16-bit aligned and a 4-
bit per pixel format must be 8-bit aligned.
Chrom-ART Accelerator controller (DMA2D)
24 23 22 21
Res. Res. Res. Res.
8 7 6
Res. Res. Res. CCEIF CCTCIF CAECIF CTWIF
rc_w1
24 23 22
MA[31:16]
rw rw rw
8 7 6
MA[15:0]
rw rw rw
RM0432 Rev 6
20 19 18
Res. Res. Res.
5 4 3 2
rc_w1 rc_w1 rc_w1
21 20 19 18
rw rw rw rw
5 4 3 2
rw rw rw rw
17 16
Res. Res.
1 0
CTCIF CTEIF
rc_w1 rc_w1
17 16
rw rw
1 0
rw rw
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