ST STM32L4+ Series Reference Manual page 315

RM0432
Bits 4:3 ADFSDMSEL: Digital filter for sigma delta modulator audio clock source selection
Set and reset by software.
Bit 2 DFSDMSEL: Digital filter for sigma delta modulator kernel clock source selection
Set and reset by software.
Bits 1:0 I2C4SEL[1:0]: I2C4 clock source selection
These bits are set and cleared by software to select the I2C4 clock source.
6.4.33 OCTOSPI delay configuration register (RCC_DLYCFGR)
Address: 0xA4h
Reset value: 0x0000 0000h
Access: no wait state, word, half-word and byte access
This register allows to configure OCTOSPI's delay cell.
31 30 29
Res. Res. Res.
15 14 13
Res. Res. Res.
00: SAI1clock selected as DFSDM audio clock
01: HSI clock selected as DFSDM audio clock
10: MSI clock selected as DFSDM audio clock
11: reserved
0: APB2 clock (PCLK2) selected as DFSDM kernel clock
1: System clock selected as DFSDM kernel clock
00: PCLK selected as I2C4 clock
01: System clock (SYSCLK) selected as I2C4 clock
10: HSI16 clock selected as I2C4 clock
11: reserved
28 27 26 25
Res. Res. Res. Res.
12 11 10 9
Res. Res. Res. Res.
24 23 22
Res. Res. Res.
8 7 6
Res. OCTOSPI2_DLY
rw rw
RM0432 Rev 6
Reset and clock control (RCC)
21 20 19 18
Res. Res. Res. Res.
5 4 3 2
OCTOSPI1_DLY
rw rw rw rw
17 16
Res. Res.
1 0
rw rw
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