ST STM32L4+ Series Reference Manual page 142

Embedded Flash memory (FLASH)
corrupted data from the Flash when the memory organization is changed, any access
(either CPU or DMAs) to Flash memory should be avoided before reprogramming.
•
Disable Instruction/data caches and/or prefetch if they are enabled (reset PRFTEN and
ICEN/DCEN bits in the FLASH_ACR register).
• Flush instruction and data cache by setting the DCRST/ICRST bits in the FLASH_ACR
register.
•
Set the DBANK option bit and clear all the WRP write protection (follow user option
modification and option bytes loader procedure).
–
–
–
–
The new software is ready to be run using the bank configuration.
De-activating Dual-bank mode (switching from DBANK=1 to DBANK=0)
When switching from one Flash mode to another (for example from single to dual-bank) it is
recommended to execute the code from the SRAM or use the bootloader. To avoid reading
corrupted data from the Flash when the memory organization is changed, any access
(either CPU or DMAs) to Flash memory should be avoided before reprogramming.
•
Disable Instruction/data caches and/or prefetch if they are enabled (reset PRFTEN and
ICEN/DCEN bits in the FLASH_ACR register).
•
Flush instruction and data cache by setting the DCRST/ICRST bits in the FLASH_ACR
register.
•
Clear the DBANK option bit and all WRP write protection (follow user option
modification and option bytes loader procedure).
–
–
–
The new software is ready to be run using the bank configuration.
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Once OBL is done with DBANK=0, perform a mass erase.
Start a new programing of code in 64 bits mode with DBANK=0 memory mapping.
Set the new WRP/PCROP with DBANK=0 scheme if needed.
Set PRFTEN and ICEN/DCEN if needed.
Once OBL is done with DBANK=0, perform a mass erase.
Start a new programing of code in 128 bits mode with DBANK=0 memory mapping
Set the new WRP/PCROP with DBANK=0 scheme if needed. Set PRFTEN and
ICEN/DCEN if needed.
RM0432 Rev 6
RM0432