ST STM32L4+ Series Reference Manual page 250

Reset and clock control (RCC)
The enable bit of each PLL output clock (PLLPEN, PLLQEN, PLLREN, PLLSAI1PEN,
PLLSAI1QEN, PLLSAI1REN, PLLSAI2PEN and PLLSAI2REN) can be modified at any time
without stopping the corresponding PLL. PLLREN cannot be cleared if PLLCLK is used as
system clock.
6.2.6 LSE clock
The LSE crystal is a 32.768 kHz Low Speed External crystal or ceramic resonator. It has the
advantage of providing a low-power but highly accurate clock source to the real-time clock
peripheral (RTC) for clock/calendar or other timing functions.
The LSE crystal is switched on and off using the LSEON bit in
register (RCC_BDCR). The crystal oscillator driving strength can be changed at runtime
using the LSEDRV[1:0] bits in the
the best compromise between robustness and short start-up time on one side and low-
power-consumption on the other side. The LSE drive can be decreased to the lower drive
capability (LSEDRV=00) when the LSE is ON. However, once LSEDRV is selected, the
drive capability can not be increased if LSEON=1.
The LSERDY flag in the
the LSE crystal is stable or not. At startup, the LSE crystal output clock signal is not released
until this bit is set by hardware. An interrupt can be generated if enabled in the
interrupt enable register
Distribution of the external 32 kHz clock (LSE) outside the RTC block could be disabled by
setting LSESYSDIS bit in Backup domain control register (RCC_BDCR) to reduce power
consumption. Propagation is stopped regardless the use of LSE by other peripherals. This
feature is present only on STM32L4P5xx and STM32L4Q5xx devices.
External source (LSE bypass)
In this mode, an external clock source must be provided. It can have a frequency of up to
1 MHz. You select this mode by setting the LSEBYP and LSEON bits in the
clocks enable in Sleep and Stop modes register
signal (square, sinus or triangle) with ~50 % duty cycle has to drive the OSC32_IN pin while
the OSC32_OUT pin can be used as GPIO. See
6.2.7 LSI clock
The LSI RC acts as a low-power clock source that can be kept running in Stop and Standby
mode for the independent watchdog (IWDG) RTC. The clock frequency is 32 kHz. For more
details, refer to the electrical characteristics section of the datasheets.
The LSI RC can be switched on and off using the LSION bit in the
(RCC_CSR).
The LSIRDY flag in the
stable or not. At startup, the clock is not released until this bit is set by hardware. An
interrupt can be generated if enabled in the
250/2301
Backup domain control register (RCC_BDCR)
Backup domain control register (RCC_BDCR)
(RCC_CIER).
Control/status register (RCC_CSR)
Clock interrupt enable register
RM0432 Rev 6
Backup domain control
(RCC_AHB1SMENR). The external clock
Figure 19.
Control/status register
indicates if the LSI oscillator is
RM0432
to obtain
indicates whether
Clock
AHB1 peripheral
(RCC_CIER).