ST STM32L4+ Series Reference Manual page 931

RM0432
Burst mode
In this mode, the entire active pixel line is buffered into a FIFO and transmitted in a single
packet with no interruptions. This transmission mode requires that the DPI Pixel FIFO has
the capacity to store a full line of active pixel data inside it. This mode is optimally used
when the difference between the pixel required bandwidth and DSI link bandwidth is
significant, it enables the DSI Host to quickly dispatch the entire active video line in a single
burst of data and then return to Low-power mode.
Non-Burst mode
In this mode, the processor uses the partitioning properties of the DSI Host to divide the
video line transmission into several DSI packets. This is done to match the pixel required
bandwidth with the DSI link bandwidth. With this mode, the controller configuration does not
require a full line of pixel data to be stored inside the LTDC interface pixel FIFO. It requires
only the content of one video packet.
Guidelines for selecting the Burst or Non-Burst mode
Selecting the Burst and Non-Burst mode is mainly dependent on the system configuration
and the device requirements. Choose the video transmission mode that suits the application
scenario. The Burst mode is more beneficial because it increases the probability of the link
spending more time in the Low-Power mode, decreasing power consumption. However, the
following conditions should be met for availing the maximum benefits from the Burst mode
of operation:
•
The DSI Host core should have sufficient pixel memory to store an entire pixel line to
avoid the overflow of the internal FIFOs.
•
The display device should support receiving a full pixel line in a single packet burst to
avoid the overflow on the reception buffer.
•
The DSI output bandwidth should be higher than the LTDC interface input bandwidth in
a relation that enables the link to go to Low-Power once per line.
If the system cannot meet these requirements, it is likely that the pixel data will be lost
causing the malfunctioning of the display device while using the Burst mode. These errors
are related to the capabilities of the system to store the temporary pixel data.
If all the conditions for using the Burst mode cannot be met, use the Non-Burst mode to
avoid the errors caused by the Burst mode. The Non-Burst mode provides a better matching
of rates for pixel transmission, enabling:
•
Only a certain amount of pixels to be stored in the memory and not requiring a full pixel
line (lesser LTDC interface RAM requirements in the DSI Host).
•
Operation with devices that support only a small amount of pixel buffering (less than a
full pixel line).
The DSI Non-Burst mode should be configured in such way that the DSI output pixel ratio
matches with the LTDC interface input pixel ratio, reducing the memory requirements on
both host and/or device side. This is achieved by dividing a pixel line into several chunks of
pixels and optionally interleaving them with null packets.
The following equations show how the DSI Host core transmission parameters should be
programmed in Non-Burst mode to match the DSI link pixel output ratio (left hand side of the
"=" sign) and LTDC interface pixel input (right hand side of the "=" sign).
DSI Host (DSIHOST) applied to STM32L4R9xx and STM32L4S9xx only
RM0432 Rev 6 931/2301
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