ST STM32L4+ Series Reference Manual page 1085

RM0432 True random number generator (RNG) applied to STM32L4P5xx and STM32L4Q5xx only
the case a seed error occurred between RNG_SR polling and RND_DR output reading (rare
event).
If the random number generation period is a concern to the application and if NIST
compliance is not required it is possible to select a faster RNG configuration by using the
RNG configuration "B", described in
in random number generation speed is summarized in
Low-power operations
If the power consumption is a concern to the application, low-power strategies can be used,
as described in
Software post-processing
No specific software post-processing/conditioning is expected to meet the AIS-31 or NIST
SP800-90B approvals.
Built-in health check functions are described in
33.3.6 RNG clocking
The RNG runs on two different clocks: the AHB bus clock and a dedicated RNG clock.
The AHB clock is used to clock the AHB banked registers and conditioning component. The
RNG clock, coupled with a programmable divider (see CLKDIV bitfield in the RNG_CR
register) is used for noise source sampling. Recommended clock configurations are detailed
in Section 33.6: RNG entropy source
Note: When the CED bit in the RNG_CR register is set to "0", the RNG clock frequency before
internal divider should be higher than AHB clock frequency divided by 32, otherwise the
clock checker always flags a clock error (CECS=1 in the RNG_SR register).
See Section 33.3.1: RNG block diagram
33.3.7 Error management
In parallel to random number generation an health check block verifies the correct noise
source behavior and the frequency of the RNG source clock as detailed in this section.
Associated error state is also described.
Clock error detection
When the clock error detection is enabled (CED = 0) and if the RNG clock frequency is too
low, the RNG sets to "1" both the CEIS and CECS bits to indicate that a clock error
occurred. In this case, the application should check that the RNG clock is configured
correctly (see
flag. The CECS bit is automatically cleared when clocking condition is normal.
Note: The clock error has no impact on generated random numbers, i.e. application can still read
RNG_DR register.
CEIS is set only when CECS is set to "1" by RNG.
Section 33.3.8: RNG low-power
Section 33.3.6: RNG
RM0432 Rev 6
Section 33.6: RNG entropy source
Section 33.5: RNG processing
usage.
Section 33.3.3: Random number
validation.
for details (AHB and RNG clock domains).
clocking) and then it must clear the CEIS bit interrupt
validation. The gain
time.
generation.
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