ST STM32L4+ Series Reference Manual page 429

RM0432
Once each pixel has been converted into 32 bits by their respective PFCs, they are blended
together, and the resulting 32-bit pixel value is encoded by the output PFC according to the
specified output format, and the data are written into the destination memory location
pointed by DMA2D_OMAR.
Configuration error detection
The DMA2D checks that the configuration is correct before any transfer. The configuration
error interrupt flag is set by hardware when a wrong configuration is detected when a new
transfer/automatic loading starts. An interrupt is then generated if the CEIE bit of the
DMA2D_CR is set.
The wrong configurations that can be detected are listed below:
•
Foreground CLUT automatic loading: MA bits of DMA2D_FGCMAR are not aligned
with CCM of DMA2D_FGPFCCR.
• Background CLUT automatic loading: MA bits of DMA2D_BGCMAR are not aligned
with CCM of DMA2D_BGPFCCR
•
Memory transfer (except in register-to-memory mode and except in memory-to-
memory mode with blending and fixed color FG): MA bits of DMA2D_FGMAR are not
aligned with CM of DMA2D_FGPFCCR
•
Memory transfer (except in register-to-memory mode and except in memory-to-
memory mode with blending and fixed color FG): CM bits of DMA2D_FGPFCCR are
invalid
•
Memory transfer (except in register-to-memory mode and except in memory-to-
memory mode with blending and fixed color FG): PL bits of DMA2D_NLR are odd while
CM of DMA2D_FGPFCCR is A4 or L4
•
Memory transfer (except in register-to-memory mode and except in memory-to-
memory mode with blending and fixed color FG): LO bits of DMA2D_FGOR are odd
while CM of DMA2D_FGPFCCR is A4 or L4 and LOM bit of the DMA2D_CR is pixel
mode
•
Memory transfer (only in blending mode and except in memory-to-memory mode with
blending and fixed color FG): MA bits of DMA2D_BGMAR are not aligned with the CM
of DMA2D_BGPFCCR
•
Memory transfer: (only in blending mode and in blending with fixed color FG mode) CM
bits of DMA2D_BGPFCCR are invalid
•
Memory transfer (only in blending mode and in blending with fixed color FG mode): PL
bits of DMA2D_NLR odd while CM of DMA2D_BGPFCCR is A4 or L4
•
Memory transfer (only in blending mode and in blending with fixed color FG mode): LO
bits of DMA2D_BGOR are odd while CM of DMA2D_BGPFCCR is A4 or L4 and LOM
bit of the DMA2D_CR is pixel mode
•
Memory transfer (except in memory to memory mode): MA bits of DMA2D_OMAR are
not aligned with CM bits of DMA2D_OPFCCR.
• Memory transfer (except in memory to memory mode): CM bits of DMA2D_OPFCCR
are invalid
•
Memory transfer with byte swapping: PL bits of DMA2D_NLR are odd or MA bits of the
DMA2D_OMAR are odd or LO in bytes (resulting from LOM bit of the DMA2D_CR and
LO bits of DMA2D_OOR values) are odd while SB bit of DMA2D_OPFCCR is set
•
Memory transfer: NL bits of DMA2D_NLR = 0
Chrom-ART Accelerator controller (DMA2D)
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