ST STM32L4+ Series Reference Manual page 864

Digital filter for sigma delta modulators (DFSDM)
Bits 15:12 BKSCD[3:0]: Break signal assignment for short-circuit detector on channel y
BKSCD[i] = 0: Break i signal not assigned to short-circuit detector on channel y
BKSCD[i] = 1: Break i signal assigned to short-circuit detector on channel y
Bits 11:8 Reserved, must be kept at reset value.
Bits 7:0 SCDT[7:0]: short-circuit detector threshold for channel y
These bits are written by software to define the threshold counter for the short-circuit detector. If this
value is reached, then a short-circuit detector event occurs on a given channel.
28.7.4 DFSDM channel y watchdog filter data register
(DFSDM_CHyWDATR)
This register contains the data resulting from the analog watchdog filter associated to the
input channel y.
Address offset: 0x0C + 0x20 * y, (y = 0 to 7)
Reset value: 0x0000 0000
31 30 29 28
Res. Res. Res. Res.
15 14 13 12
r r r r
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:0 WDATA[15:0]: Input channel y watchdog data
Data converted by the analog watchdog filter for input channel y. This data is continuously converted
(no trigger) for this channel, with a limited resolution (OSR=1..32/sinc order = 1..3).
28.7.5 DFSDM channel y data input register (DFSDM_CHyDATINR)
This register contains 16-bit input data to be processed by DFSDM filter module. Write
access can be either word access (32-bit) or half-word access (16-bit).
Address offset: 0x10 + 0x20 * y, (y = 0 to 7)
Reset value: 0x0000 0000
31 30 29 28
rw rw rw rw
15 14 13 12
rw rw rw rw
864/2301
27 26 25 24
Res. Res. Res. Res.
11 10 9 8
WDATA[15:0]
r r r r
27 26 25 24
INDAT1[15:0]
rw rw rw rw
11 10 9 8
INDAT0[15:0]
rw rw rw rw
RM0432 Rev 6
23 22 21 20
Res. Res. Res. Res.
7 6 5 4
r r r r
23 22 21 20
rw rw rw rw
7 6 5 4
rw rw rw rw
RM0432
19 18 17 16
Res. Res. Res. Res.
3 2 1 0
r r r
19 18 17 16
rw rw rw rw
3 2 1 0
rw rw rw rw
r