ST STM32L4+ Series Reference Manual page 288

Reset and clock control (RCC)
Bit 18 RNGEN: Random Number Generator clock enable
Set and cleared by software.
0: Random Number Generator clock disabled
1: Random Number Generator clock enabled
Bit 17 HASHEN: HASH clock enable
Set and cleared by software
0: HASH clock disabled
1: HASH clock enabled
Bit 16 AESEN: AES accelerator clock enable
Set and cleared by software.
0: AES clock disabled
1: AES clock enabled
Bit 15 PKAEN: PKA clock enable
Set and cleared by software.
0: PKA clock disabled
1: PKA clock enabled
Bit 14 DCMIEN: DCMI or PSSI clock enable (DCMI or PSSI depending on which interface is active)
Set and cleared by software
0: DCMI/PSSI clock disabled
1: DCMI/PSSI clock enabled
Bit 13 ADCEN: ADC clock enable
Set and cleared by software.
0: ADC clock disabled
1: ADC clock enabled
Bit 12 OTGFSEN: OTG full speed clock enable
Set and cleared by software.
0: USB OTG full speed clock disabled
1: USB OTG full speed clock enabled
Bits 11:9 Reserved, must be kept at reset value.
Bit 8 GPIOIEN: IO port I clock enable
Set and cleared by software
0: IO port I clock disabled
1: IO port I clock enabled
Bit 7 GPIOHEN: IO port H clock enable
Set and cleared by software.
0: IO port H clock disabled
1: IO port H clock enabled
Bit 6 GPIOGEN: IO port G clock enable
Set and cleared by software.
0: IO port G clock disabled
1: IO port G clock enabled
Bit 5 GPIOFEN: IO port F clock enable
Set and cleared by software.
0: IO port F clock disabled
1: IO port F clock enabled
288/2301 RM0432 Rev 6
RM0432