Table of Contents
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STM32 Cortex
Introduction
This programming manual provides information for application and system-level software
developers. It gives a full description of the STM32 Cortex
model, instruction set and core peripherals. The applicable products are listed in the table
below.
The Cortex
STM32H7 Series, STM32L4 Series, STM32L4+ Series, STM32WB Series, STM32WL
Series and STM32MP1 Series, is a high performance 32-bit processor designed for the
microcontroller and microprocessor market. It offers significant benefits to developers,
including:
• Outstanding processing performance combined with fast interrupt handling
• Enhanced system debug with extensive breakpoint and trace capabilities
• Efficient processor core, system and memories
• Ultra-low power consumption with integrated sleep modes
• Platform security
Microcontrollers
Microprocessors
Reference documents
Available from STMicroelectronics web site www.st.com:
•
STM32F3 Series, STM32F4 Series, STM32G4 Series, STM32H7 Series, STM32L4
Series, STM32L4+ Series, STM32MP1 Series, STM32WB Series and STM32WL
Series datasheets
•
STM32F3 Series, STM32F4 Series, STM32G4 Series, STM32H7 Series, STM32L4
Series, STM32L4+ Series, STM32MP1 Series, STM32WB Series and STM32WL
Series reference manuals
December 2019
®
-M4 MCUs and MPUs programming manual
®
-M4 processor used in STM32F3 Series, STM32F4 Series, STM32G4 Series,
Table 1. Applicable products
Type
STM32F3 Series, STM32F4 Series, STM32G4 Series
STM32L4 Series, STM32L4+ Series, STM32WB Series, STM32WL Series
STM32MP1 Series
Programming manual
Product series
PM0214 Rev 9
PM0214
®
-M4 processor programming
,
STM32H7 Series,
1/262
www.st.com
1
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Table of Contents
Related Manuals for ST STM32H7 Series
Summary of Contents for ST STM32H7 Series
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Page 1: Table 1. Applicable Products
The Cortex -M4 processor used in STM32F3 Series, STM32F4 Series, STM32G4 Series, STM32H7 Series, STM32L4 Series, STM32L4+ Series, STM32WB Series, STM32WL Series and STM32MP1 Series, is a high performance 32-bit processor designed for the microcontroller and microprocessor market. It offers significant benefits to developers, including: •... -
Page 2: Table Of Contents
Contents PM0214 Contents About this document ........12 Typographical conventions . - Page 3 PM0214 Contents Fault handling ..........44 2.4.1 Fault types .
- Page 4 Contents PM0214 3.5.3 ASR, LSL, LSR, ROR, and RRX ......86 3.5.4 CLZ .
- Page 5 PM0214 Contents 3.7.2 SSAT16 and USAT16 ........127 3.7.3 QADD and QSUB .
- Page 6 Contents PM0214 3.10.18 VMOV Arm Core register to scalar ......168 3.10.19 VMRS ..........169 3.10.20 VMSR .
- Page 7 PM0214 Contents 4.2.9 MPU region attribute and size register (MPU_RASR) ... . . 204 4.2.10 MPU register map ........206 Nested vectored interrupt controller (NVIC) .
- Page 8 Contents PM0214 4.5.3 SysTick current value register (STK_VAL) ..... . 249 4.5.4 SysTick calibration value register (STK_CALIB) ....250 4.5.5 SysTick design hints and tips .
- Page 9 PM0214 List of tables List of tables Table 1. Applicable products ............1 Table 2.
- Page 10 List of tables PM0214 Table 49. NVIC register map and reset values ......... 219 Table 50.
- Page 11 PM0214 List of figures List of figures Figure 1. STM32 Cortex-M4 implementation ......... . . 13 Figure 2.
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Page 12: About This Document
About this document PM0214 About this document This document provides the information required for application and system-level software development. It does not provide information on debug components, features, or operation. This material is for microcontroller software and hardware engineers, including those who have no experience of Arm products. -
Page 13: About The Stm32 Cortex-M4 Processor And Core Peripherals
PM0214 About this document read/clear (rc_w1) Software can read as well as clear this bit by writing 1. Writing ‘0’ has no effect on the bit value. read/clear (rc_w0) Software can read as well as clear this bit by writing 0. Writing ‘1’... -
Page 14: System Level Interface
About this document PM0214 To facilitate the design of cost-sensitive devices, the Cortex-M4 processor implements tightly-coupled system components that reduce processor area while significantly improving interrupt handling and system debug capabilities. The Cortex-M4 processor implements a ® version of the Thumb instruction set based on Thumb-2 technology, ensuring high code density and reduced program memory requirements. -
Page 15: Cortex-M4 Processor Features And Benefits Summary
PM0214 About this document 1.3.3 Cortex-M4 processor features and benefits summary • Tight integration of system peripherals reduces area and development costs • Thumb instruction set combines high code density with 32-bit performance • IEEE754-compliant single-precision FPU implemented in all STM32 Cortex-M4 microcontrollers •... -
Page 16: Cortex-M4 Core Peripherals
About this document PM0214 1.3.4 Cortex-M4 core peripherals The peripherals are: Nested vectored interrupt controller The nested vectored interrupt controller (NVIC) is an embedded interrupt controller that supports low latency interrupt processing. System control block The system control block (SCB) is the programmer’s model interface to the processor. It provides system implementation information and system control, including configuration, control, and reporting of system exceptions. -
Page 17: The Cortex-M4 Processor
PM0214 The Cortex-M4 processor The Cortex-M4 processor Programmers model This section describes the Cortex-M4 programmer’s model. In addition to the individual core register descriptions, it contains information about the processor modes and privilege levels for software execution and stacks. 2.1.1 Processor mode and privilege levels for software execution The processor modes are: Thread mode: Used to execute application software. -
Page 18: Core Registers
The Cortex-M4 processor PM0214 Table 2. Summary of processor mode, execution privilege level, and stack usage Processor Used to Privilege level for Stack used mode execute software execution Thread Applications Privileged or unprivileged Main stack or process stack Handler Exception handlers Always privileged Main stack 1. - Page 19 PM0214 The Cortex-M4 processor Table 3. Core register set summary (continued) Required Reset Name Type Description privilege value read-write Privileged 0x01000000 Program status register on page 19 Application program status register on ASPR read-write Either Unknown page 21 Interrupt program status register on IPSR read-only Privileged...
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Page 20: Table 4. Psr Register Combinations
The Cortex-M4 processor PM0214 These registers are mutually exclusive bitfields in the 32-bit PSR. The bit assignment is shown in Figure 3 Figure Figure 3. APSR, IPSR and EPSR bit assignment Figure 4. PSR bit assignment Access these registers individually or as a combination of any two or all three registers, using the register name as an argument to the MSR or MRS instructions. -
Page 21: Table 5. Apsr Bit Definitions
PM0214 The Cortex-M4 processor Application program status register The APSR contains the current state of the condition flags from previous instruction executions. See the register summary in Table 3 on page 18 for its attributes. The bit assignment is: Table 5. APSR bit definitions Bits Description Bit 31... -
Page 22: Table 6. Ipsr Bit Definitions
The Cortex-M4 processor PM0214 Interrupt program status register The IPSR contains the exception type number of the current Interrupt Service Routine (ISR). See the register summary in Table 3 on page 18 for its attributes. The bit assignment is: Table 6. IPSR bit definitions Bits Description Bits 31:9... -
Page 23: Table 7. Epsr Bit Definitions
PM0214 The Cortex-M4 processor Table 7. EPSR bit definitions Bits Description Bits 31:27 Reserved. Bits 26:25, 15:10 ICI: Interruptible-continuable instruction bits, see Interruptible-continuable instructions on page IT on page 145 Bits 26:25, 15:10 IT: Indicates the execution state bits of the IT instruction, see Bit 24 T: Thumb state bit. -
Page 24: Table 8. Primask Register Bit Definitions
The Cortex-M4 processor PM0214 To access the exception mask registers use the MSR and MRS instructions, or the CPS instruction to change the value of PRIMASK or FAULTMASK. See MRS on page 186, on page 187, and CPS on page 182 for more information. -
Page 25: Table 10. Basepri Register Bit Assignment
PM0214 The Cortex-M4 processor Base priority mask register The BASEPRI register defines the minimum priority for exception processing. When BASEPRI is set to a nonzero value, it prevents the activation of all exceptions with same or lower priority level as the BASEPRI value. See the register summary in Table 3 on page 18 for its attributes. -
Page 26: Exceptions And Interrupts
The Cortex-M4 processor PM0214 Handler mode always uses the MSP, so the processor ignores explicit writes to the active stack pointer bit of the CONTROL register when in Handler mode. The exception entry and return mechanisms update the CONTROL register. In an OS environment, it is recommended that threads running in Thread mode use the process stack, and the kernel and exception handlers use the main stack. - Page 27 PM0214 The Cortex-M4 processor The CMSIS includes address definitions and data structures for the core peripherals in the Cortex-M4 processor. CMSIS simplifies software development by enabling the reuse of template code and the combination of CMSIS-compliant software components from various middleware vendors. Software vendors can expand the CMSIS to include their peripheral definitions and access functions for those peripherals.
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Page 28: Memory Model
The Cortex-M4 processor PM0214 Memory model This section describes the processor memory map, the behavior of memory accesses, and the bit-banding features. The processor has a fixed memory map that provides up to 4 GB of addressable memory. Figure 8. Memory map The regions for SRAM and peripherals include bit-band regions. -
Page 29: Memory Regions, Types And Attributes
PM0214 The Cortex-M4 processor 2.2.1 Memory regions, types and attributes The memory map and the programming of the MPU splits the memory map into regions. Each region has a defined memory type, and some regions have additional memory attributes. The memory type and attributes determine the behavior of accesses to the region. -
Page 30: Behavior Of Memory Accesses
The Cortex-M4 processor PM0214 2.2.3 Behavior of memory accesses The behavior of accesses to each region in the memory map is: Table 13. Memory access behavior Address Memory Memory Description range region type 0x00000000- Executable region for program code. Can also put Code Normal 0x1FFFFFFF... -
Page 31: Software Ordering Of Memory Accesses
PM0214 The Cortex-M4 processor 2.2.4 Software ordering of memory accesses The order of instructions in the program flow does not always guarantee the order of the corresponding memory transactions. The reason for this is that: • The processor can reorder some memory accesses to improve efficiency, providing this does not affect the behavior of the instruction sequence. -
Page 32: Bit-Banding
The Cortex-M4 processor PM0214 2.2.5 Bit-banding A bit-band region maps each word in a bit-band alias region to a single bit in the bit-band region. The bit-band regions occupy the lowest 1 Mbyte of the SRAM and peripheral memory regions. The memory map has two 32 Mbyte alias regions that map to two 1 Mbyte bit-band regions: •... -
Page 33: Figure 9. Bit-Band Mapping
PM0214 The Cortex-M4 processor Where: • Bit_word_offset is the position of the target bit in the bit-band memory region. • Bit_word_addr is the address of the word in the alias memory region that maps to the targeted bit. • Bit_band_base is the starting address of the alias region. •... -
Page 34: Memory Endianness
The Cortex-M4 processor PM0214 Reading a word in the alias region: • 0x00000000 indicates that the targeted bit in the bit-band region is set to zero • 0x00000001 indicates that the targeted bit in the bit-band region is set to 1 Directly accessing a bit-band region Behavior of memory accesses on page 30 describes the behavior of direct byte, halfword,... - Page 35 PM0214 The Cortex-M4 processor The pairs of Load-Exclusive and Store-Exclusive instructions are: • The word instructions LDREX and STREX • The halfword instructions LDREXH and STREXH • The byte instructions LDREXB and STREXB. Software must use a Load-Exclusive instruction with the corresponding Store-Exclusive instruction.
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Page 36: Programming Hints For The Synchronization Primitives
The Cortex-M4 processor PM0214 2.2.8 Programming hints for the synchronization primitives ISO/IEC C cannot directly generate the exclusive access instructions. CMSIS provides intrinsic functions for generation of these instructions: Table 16. CMSIS functions for exclusive access instructions Instruction CMSIS function LDREX uint32_t __LDREXW (uint32_t *addr) LDREXH... -
Page 37: Exception Model
PM0214 The Cortex-M4 processor Exception model This section describes the exception model. 2.3.1 Exception states Each exception is in one of the following states: Inactive The exception is not active and not pending. Pending The exception is waiting to be serviced by the processor. An interrupt request from a peripheral or from software can change the state of the corresponding interrupt to pending. -
Page 38: Table 17. Properties Of The Different Exception Types
The Cortex-M4 processor PM0214 Bus fault A bus fault is an exception that occurs because of a memory related fault for an instruction or data memory transaction. This might be from an error detected on a bus in the memory system. Usage fault A usage fault is an exception that occurs in case of an instruction execution fault. -
Page 39: Exception Handlers
PM0214 The Cortex-M4 processor Table 17. Properties of the different exception types (continued) Exception Exception Vector address Priority Activation number number type or offset SysTick Configurable 0x0000003C Asynchronous 16 and 0 and 0x00000040 and Interrupt (IRQ) Configurable Asynchronous above above above 1. -
Page 40: Vector Table
The Cortex-M4 processor PM0214 2.3.4 Vector table The vector table contains the reset value of the stack pointer, and the start addresses, also called exception vectors, for all exception handlers. Figure 11 on page 40 shows the order of the exception vectors in the vector table. The least-significant bit of each vector must be 1, indicating that the exception handler is Thumb code. -
Page 41: Exception Priorities
PM0214 The Cortex-M4 processor 2.3.5 Exception priorities Table 17 on page 38 shows that all exceptions have an associated priority, in details: • A lower priority value indicating a higher priority • Configurable priorities for all exceptions except Reset, Hard fault, and NMI. If software does not configure any priorities, then all exceptions with a configurable priority have a priority of 0. -
Page 42: Exception Entry And Return
The Cortex-M4 processor PM0214 2.3.7 Exception entry and return Descriptions of exception handling use the following terms: Preemption When the processor is executing an exception handler, an exception can preempt the exception handler if its priority is higher than the priority of the exception being handled. -
Page 43: Figure 12. Cortex-M4 Stack Frame Layout
PM0214 The Cortex-M4 processor stack frame is the same as that of Armv7-M implementations without an FPU. Figure 12 on page 43 also shows this stack frame. Figure 12. Cortex-M4 stack frame layout Immediately after stacking, the stack pointer indicates the lowest address in the stack frame. The alignment of the stack frame is controlled via the STKALIGN bit of the Configuration Control Register (CCR). -
Page 44: Fault Handling
The Cortex-M4 processor PM0214 Exception return Exception return occurs when the processor is in Handler mode and executes one of the following instructions to load the EXC_RETURN value into the PC: • an LDM or POP instruction that loads the PC •... -
Page 45: Fault Types
PM0214 The Cortex-M4 processor 2.4.1 Fault types Table 19 shows the types of fault, the handler used for the fault, the corresponding fault status register, and the register bit that indicates that the fault has occurred. See Configurable fault status register (CFSR; UFSR+BFSR+MMFSR) on page 237 for more information about the fault status registers. -
Page 46: Fault Escalation And Hard Faults
The Cortex-M4 processor PM0214 2.4.2 Fault escalation and hard faults All faults exceptions except for hard fault have configurable exception priority, as described System handler priority registers (SHPRx) on page 233. Software can disable execution of the handlers for these faults, as described in System handler control and state register (SHCSR) on page 235. -
Page 47: Fault Status Registers And Fault Address Registers
PM0214 The Cortex-M4 processor 2.4.3 Fault status registers and fault address registers The fault status registers indicate the cause of a fault. For bus faults and memory management faults, the fault address register indicates the address accessed by the operation that caused the fault, as shown in Table Table 20. -
Page 48: Entering Sleep Mode
The Cortex-M4 processor PM0214 2.5.1 Entering sleep mode This section describes the mechanisms software can use to put the processor into sleep mode. The system can generate spurious wakeup events, for example a debug operation that wakes up the processor. Therefore software must be able to put the processor back into sleep mode after such an event. -
Page 49: External Event Input / Extended Interrupt And Event Input
PM0214 The Cortex-M4 processor Wakeup from WFE The processor wakes up if: • it detects an exception with sufficient priority to cause exception entry • it detects an external event signal, see Section 2.5.3: External event input / extended interrupt and event input •... -
Page 50: The Stm32 Cortex-M4 Instruction Set
The STM32 Cortex-M4 instruction set PM0214 The STM32 Cortex-M4 instruction set This chapter is the reference material for the Cortex-M4 instruction set description in a User Guide. The following sections give general information: Section 3.1: Instruction set summary on page 50 Section 3.2: CMSIS intrinsic functions on page 58 Section 3.3: About the instruction descriptions on page 60 Each of the following sections describes a functional group of Cortex-M4 instructions. - Page 51 PM0214 The STM32 Cortex-M4 instruction set Table 21. Cortex-M4 instructions (continued) Mnemonic Operands Brief description Flags Page AND, ANDS {Rd,} Rn, Op2 Logical AND N,Z,C 3.5.2 on page 85 ASR, ASRS Rd, Rm, <Rs|#n> Arithmetic shift right N,Z,C 3.5.3 on page 86 label Branch —...
- Page 52 The STM32 Cortex-M4 instruction set PM0214 Table 21. Cortex-M4 instructions (continued) Mnemonic Operands Brief description Flags Page Load register exclusive with LDREXB Rt, [Rn] — 3.4.8 on page 79 byte Load register exclusive with LDREXH Rt, [Rn] — 3.4.8 on page 79 halfword LDRH, Rt, [Rn, #offset]...
- Page 53 PM0214 The STM32 Cortex-M4 instruction set Table 21. Cortex-M4 instructions (continued) Mnemonic Operands Brief description Flags Page QDADD {Rd,} Rn, Rm Saturating add 3.7.5 on page 130 Saturating double and QDSUB {Rd,} Rn, Rm 3.7.5 on page 130 subtract Saturating subtract and add QSAX {Rd,} Rn, Rm 3.7.4 on page 129...
- Page 54 The STM32 Cortex-M4 instruction set PM0214 Table 21. Cortex-M4 instructions (continued) Mnemonic Operands Brief description Flags Page Signed multiply with SMLAL RdLo, RdHi, Rn, Rm accumulate (32 x 32 + 64), 64- — 3.6.2 on page 111 bit result SMLALBB, Signed multiply accumulate SMLALBT, RdLo, RdHi, Rn, Rm...
- Page 55 PM0214 The STM32 Cortex-M4 instruction set Table 21. Cortex-M4 instructions (continued) Mnemonic Operands Brief description Flags Page STRD Rt, Rt2, [Rn, #offset] Store register two words — 3.4.2 on page 71 STREX Rd, Rt, [Rn, #offset] Store register exclusive — 3.4.8 on page 79 STREXB Rd, Rt, [Rn]...
- Page 56 The STM32 Cortex-M4 instruction set PM0214 Table 21. Cortex-M4 instructions (continued) Mnemonic Operands Brief description Flags Page UDIV {Rd,} Rn, Rm Unsigned divide — 3.6.3 on page 112 Unsigned multiply accumulate UMAAL RdLo, RdHi, Rn, Rm accumulate long (32 x 32 + 32 —...
- Page 57 PM0214 The STM32 Cortex-M4 instruction set Table 21. Cortex-M4 instructions (continued) Mnemonic Operands Brief description Flags Page Compare two floating-point VCMP.F32 Sd, <Sm | #0.0> registers, or one floating-point FPSCR 3.10.3 on page 153 register and zero Compare two floating-point registers, or one floating-point VCMPE.F32 Sd, <Sm | #0.0>...
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Page 58: Cmsis Intrinsic Functions
The STM32 Cortex-M4 instruction set PM0214 Table 21. Cortex-M4 instructions (continued) Mnemonic Operands Brief description Flags Page Copy Arm core register to 3.10.15 on page VMOV Dd[x], Rt — scalar Copy scalar to Arm core 3.10.16 on page VMOV Rt, Dn[x] —... -
Page 59: Table 22. Cmsis Intrinsic Functions To Generate Some Cortex-M4 Instructions
PM0214 The STM32 Cortex-M4 instruction set Table 22. CMSIS intrinsic functions to generate some Cortex-M4 instructions Instruction CMSIS intrinsic function CPSIE I void __enable_irq(void) CPSID I void __disable_irq(void) CPSIE F void __enable_fault_irq(void) CPSID F void __disable_fault_irq(void) void __ISB(void) void __DSB(void) void __DMB(void) uint32_t __REV(uint32_t int value) REV16... -
Page 60: About The Instruction Descriptions
The STM32 Cortex-M4 instruction set PM0214 About the instruction descriptions The following sections give more information about using the instructions: • Operands on page 60 • Restrictions when using PC or SP on page 60 • Flexible second operand on page 60 •... - Page 61 PM0214 The STM32 Cortex-M4 instruction set Constant You specify an operand2 constant in the form #constant, where constant can be: • Any constant that can be produced by shifting an 8-bit value left by any number of bits within a 32-bit word. •...
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Page 62: Shift Operations
The STM32 Cortex-M4 instruction set PM0214 3.3.4 Shift operations Register shift operations move the bits in a register left or right by a specified number of bits, the shift length. Register shift can be performed: • Directly by the instructions ASR, LSR, LSL, ROR, and RRX. The result is written to a destination register. -
Page 63: Figure 14. Lsr #3
PM0214 The STM32 Cortex-M4 instruction set Logical shift right by n bits moves the left-hand 32-n bits of the Rm register to the right by n places, into the right-hand 32-n bits of the result. And it sets the left-hand n bits of the result to 0 (see Figure 14). -
Page 64: Figure 16. Ror #3
The STM32 Cortex-M4 instruction set PM0214 Rotate right by n bits moves the left-hand 32-n bits of the Rm register to the right by n places, into the right-hand 32-n bits of the result. It also moves the right-hand n bits of the register into the left-hand n bits of the result (see Figure 16). -
Page 65: Address Alignment
PM0214 The STM32 Cortex-M4 instruction set 3.3.5 Address alignment An aligned access is an operation where a word-aligned address is used for a word, dual word, or multiple word access, or where a halfword-aligned address is used for a halfword access. - Page 66 The STM32 Cortex-M4 instruction set PM0214 Conditional execution is available by using conditional branches or by adding condition code suffixes to instructions. See Table 24: Condition code suffixes on page 67 for a list of the suffixes to add to instructions to make them conditional instructions. The condition code suffix enables the processor to test a condition based on the flags.
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Page 67: Table 24. Condition Code Suffixes
PM0214 The STM32 Cortex-M4 instruction set Condition code suffixes The instructions that can be conditional have an optional condition code, shown in syntax descriptions as {cond}. Conditional execution requires a preceding IT instruction. An instruction with a condition code is only executed if the condition code flags in the APSR meet the specified condition. -
Page 68: Instruction Width Selection
The STM32 Cortex-M4 instruction set PM0214 CMPGT R2, R3; if 'greater than', compare R2 and R3, setting flags MOVGT R4, R5 ; if still 'greater than', do R4 = R5 3.3.8 Instruction width selection There are many instructions that can generate either a 16-bit encoding or a 32-bit encoding depending on the specified operands and destination register. -
Page 69: Memory Access Instructions
PM0214 The STM32 Cortex-M4 instruction set Memory access instructions Table 25 shows the memory access instructions: Table 25. Memory access instructions Mnemonic Brief description Load PC-relative address ADR on page 70 CLREX Clear exclusive CLREX on page 80 LDM{mode} Load multiple registers LDM and STM on page 76 LDR{type} Load register using immediate offset... -
Page 70: Adr
The STM32 Cortex-M4 instruction set PM0214 3.4.1 Load PC-relative address. Syntax ADR{cond} Rd, label Where: • ‘cond’ is an optional condition code (see Conditional execution on page • ‘Rd’ is the destination register • ‘label’ is a PC-relative expression (see PC-relative expressions on page Operation ADR determines the address by adding an immediate value to the PC. -
Page 71: Ldr And Str, Immediate Offset
PM0214 The STM32 Cortex-M4 instruction set 3.4.2 LDR and STR, immediate offset Load and Store with immediate offset, pre-indexed immediate offset, or post-indexed immediate offset. Syntax op{type}{cond} Rt, [Rn {, #offset}]; immediate offset op{type}{cond} Rt, [Rn, #offset]!; pre-indexed op{type}{cond} Rt, [Rn], #offset; post-indexed opD{cond} Rt, Rt2, [Rn {, #offset}];... -
Page 72: Table 26. Immediate, Pre-Indexed And Post-Indexed Offset Ranges
The STM32 Cortex-M4 instruction set PM0214 The value to load or store can be a byte, halfword, word, or two words. Bytes and halfwords can either be signed or unsigned (see Address alignment on page 65). Table 26 shows the range of offsets for immediate, pre-indexed and post-indexed forms. Table 26. -
Page 73: Ldr And Str, Register Offset
PM0214 The STM32 Cortex-M4 instruction set 3.4.3 LDR and STR, register offset Load and Store with register offset. Syntax op{type}{cond} Rt, [Rn, Rm {, LSL #n}] Where: • ‘op’ is either LDR (load register) or STR (store register). • ‘type’ is one of the following: B: Unsigned byte, zero extends to 32 bits on loads. -
Page 74: Ldr And Str, Unprivileged
The STM32 Cortex-M4 instruction set PM0214 ; to a word value and put it in R0 STR R0, [R1, R2, LSL #2]; stores R0 to an address equal to sum of R1 ; and four times R2 3.4.4 LDR and STR, unprivileged Load and Store with unprivileged access. -
Page 75: Ldr, Pc-Relative
PM0214 The STM32 Cortex-M4 instruction set 3.4.5 LDR, PC-relative Load register from memory. Syntax LDR{type}{cond} Rt, label LDRD{cond} Rt, Rt2, label; load two words Where: • ‘type’ is one of the following: B: Unsigned byte, zero extends to 32 bits. SB: Signed byte, sign extends to 32 bits. -
Page 76: Ldm And Stm
The STM32 Cortex-M4 instruction set PM0214 Condition flags These instructions do not change the flags. Examples LDR R0, LookUpTable; load R0 with a word of data from an address ; labelled as LookUpTable LDRSB R7, localdata; load a byte value from an address labelled ;... - Page 77 PM0214 The STM32 Cortex-M4 instruction set lowest numbered register using the lowest memory address and the highest number register using the highest memory address. If the writeback suffix is specified, the value of Rn + 4 * (n-1) is written back to Rn. For LDMDB, LDMEA, STMDB, and STMFD the memory addresses used for the accesses are at 4-byte intervals ranging from Rn to Rn - 4 * (n-1), where n is the number of registers in reglist.
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Page 78: Push And Pop
The STM32 Cortex-M4 instruction set PM0214 3.4.7 PUSH and POP Push registers onto, and pop registers off a full-descending stack. PUSH and POP are synonyms for STMDB and LDM (or LDMIA) with the memory addresses for the access based on SP, and with the final address for the access written back to the SP. PUSH and POP are the preferred mnemonics in these cases. -
Page 79: Ldrex And Strex
PM0214 The STM32 Cortex-M4 instruction set 3.4.8 LDREX and STREX Load and Store Register Exclusive. Syntax LDREX{cond} Rt, [Rn {, #offset}] STREX{cond} Rd, Rt, [Rn {, #offset}] LDREXB{cond} Rt, [Rn] STREXB{cond} Rd, Rt, [Rn] LDREXH{cond} Rt, [Rn] STREXH{cond} Rd, Rt, [Rn] Where: •... -
Page 80: Clrex
The STM32 Cortex-M4 instruction set PM0214 Restrictions In these instructions: • Do not use PC. • Do not use SP for Rd and Rt. • For STREX, Rd must be different from both Rt and Rn. • The value of offset must be a multiple of four in the range 0-1020. Condition flags These instructions do not change the flags. -
Page 81: General Data Processing Instructions
PM0214 The STM32 Cortex-M4 instruction set General data processing instructions Table 28 shows the data processing instructions. Table 28. Data processing instructions Mnemonic Brief description Add with carry ADD, ADC, SUB, SBC, and RSB on page 83 ADD, ADC, SUB, SBC, and RSB on page 83 ADDW ADD, ADC, SUB, SBC, and RSB on page 83 Logical AND... - Page 82 The STM32 Cortex-M4 instruction set PM0214 Table 28. Data processing instructions (continued) Mnemonic Brief description SHASX Signed Halving Add and Subtract with Exchange SHASX and SHSAX on page 95 SHSAX Signed Halving Subtract and Add with exchange SHASX and SHSAX on page 95 SHSUB16 Signed Halving Subtract 16 SHSUB16 and SHSUB8 on page 96...
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Page 83: Add, Adc, Sub, Sbc, And Rsb
PM0214 The STM32 Cortex-M4 instruction set 3.5.1 ADD, ADC, SUB, SBC, and RSB Add, Add with Carry, Subtract, Subtract with Carry, and Reverse Subtract. Syntax op{S}{cond} {Rd,} Rn, Operand2 op{cond} {Rd,} Rn, #imm12; ADD and SUB only Where: • ‘op’ is one of the following: ADD: Add ADC: Add with carry SUB: Subtract... - Page 84 The STM32 Cortex-M4 instruction set PM0214 Restrictions In these instructions: • Operand2 must be neither SP nor PC • Rd can be SP only in ADD and SUB, and only with the following additional restrictions: – Rn must also be SP. –...
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Page 85: And, Orr, Eor, Bic, And Orn
PM0214 The STM32 Cortex-M4 instruction set Multiword values do not have to use consecutive registers. Specific example 5: 96-bit subtraction shows instructions that subtract a 96-bit integer contained in R9, R1, and R11 from another contained in R6, R2, and R8. The example stores the result in R6, R9, and R2. Specific example 5: 96-bit subtraction SUBS R6, R6, R9 ;... -
Page 86: Asr, Lsl, Lsr, Ror, And Rrx
The STM32 Cortex-M4 instruction set PM0214 Condition flags If S is specified, these instructions: • Update the N and Z flags according to the result. • Can update the C flag during the calculation of operand2, see Flexible second operand on page •... -
Page 87: Clz
PM0214 The STM32 Cortex-M4 instruction set Operation ASR, LSL, LSR, and ROR move the bits in the Rm register to the left or right by the number of places specified by constant n or register Rs. RRX moves the bits in Rm register to the right by 1. In all these instructions, the result is written to Rd, but the value in Rm register remains unchanged. -
Page 88: Cmp And Cmn
The STM32 Cortex-M4 instruction set PM0214 Examples CLZ R4,R9 CLZNE R2,R3 3.5.5 CMP and CMN Compare and Compare Negative. Syntax CMP{cond} Rn, Operand2 CMN{cond} Rn, Operand2 Where: • ‘cond’ is an optional condition code (see Conditional execution on page 65). •... -
Page 89: Mov And Mvn
PM0214 The STM32 Cortex-M4 instruction set 3.5.6 MOV and MVN Move and Move NOT. Syntax MOV{S}{cond} Rd, Operand2 MOV{cond} Rd, #imm16 MVN{S}{cond} Rd, Operand2 Where: • ‘S’ is an optional suffix. If S is specified, the condition code flags are updated on the result of the operation (see Conditional execution on page 65). - Page 90 The STM32 Cortex-M4 instruction set PM0214 Restrictions You can use SP and PC only in the MOV instruction, with the following restrictions: • The second operand must be a register without shift • You must not specify the S suffix When Rd is PC in a MOV instruction: •...
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Page 91: Movt
PM0214 The STM32 Cortex-M4 instruction set 3.5.7 MOVT Move Top. Syntax MOVT{cond} Rd, #imm16 Where: • ‘cond’ is an optional condition code (see Conditional execution on page 65). • ‘Rd’ is the destination register. • ‘imm16’ is a 16-bit immediate constant. Operation MOVT writes a 16-bit immediate value, imm16, to the top halfword, Rd[31:16], of its destination register. -
Page 92: Rev, Rev16, Revsh, And Rbit
The STM32 Cortex-M4 instruction set PM0214 3.5.8 REV, REV16, REVSH, and RBIT Reverse bytes and Reverse bits. Syntax op{cond} Rd, Rn Where: • ‘op’ is one of the following: REV: Reverse byte order in a word. REV16: Reverse byte order in each halfword independently. REVSH: Reverse byte order in the bottom halfword, and sign extends to 32 bits. -
Page 93: Sadd16 And Sadd8
PM0214 The STM32 Cortex-M4 instruction set 3.5.9 SADD16 and SADD8 Signed Add 16 and Signed Add 8 Syntax op{cond}{Rd,} Rn, Rm Where: • op is any of the following: SADD16: Performs two 16-bit signed integer additions. SADD8: Performs four 8-bit signed integer additions. •... -
Page 94: Shadd16 And Shadd8
The STM32 Cortex-M4 instruction set PM0214 3.5.10 SHADD16 and SHADD8 Signed Halving Add 16 and Signed Halving Add 8 Syntax op{cond}{Rd,} Rn, Rm Where: • op is any of the following: SHADD16: Signed halving add 16. SHADD8: Signed halving add 8. •... -
Page 95: Shasx And Shsax
PM0214 The STM32 Cortex-M4 instruction set 3.5.11 SHASX and SHSAX Signed Halving Add and Subtract with Exchange / Signed Halving Subtract and Add with Exchange. Syntax op{cond} {Rd}, Rn, Rm Where: • op is any of the following: SHASX: Add and subtract with exchange and halving. SHSAX: Subtract and add with exchange and halving. -
Page 96: Shsub16 And Shsub8
The STM32 Cortex-M4 instruction set PM0214 ; R4 and writes halved result to bottom halfword of R7 SHSAX R0, R3, R5 ; Subtracts bottom halfword of R5 from top halfword ; of R3 and writes halved result to top halfword of R0 ;... -
Page 97: Ssub16 And Ssub8
PM0214 The STM32 Cortex-M4 instruction set ; and writes to corresponding byte in R4. 3.5.13 SSUB16 and SSUB8 Signed Subtract 16 and Signed Subtract 8 Syntax op{cond}{Rd,} Rn, Rm Where: • op is one of the following: SSUB16: Performs two 16-bit signed integer subtractions. SSUB8: Performs four 8-bit signed integer subtractions. -
Page 98: Sasx And Ssax
The STM32 Cortex-M4 instruction set PM0214 3.5.14 SASX and SSAX Signed Add and Subtract with Exchange and Signed Subtract and Add with Exchange. Syntax op{cond} {Rd}, Rm, Rn Where: • op is any of the following: SASX: Signed add and subtract with exchange. SSAX: Signed subtract and add with exchange. -
Page 99: Tst And Teq
PM0214 The STM32 Cortex-M4 instruction set ; Adds top halfword of R3 with bottom halfword of R2 and ; writes to top halfword of R7. 3.5.15 TST and TEQ Test bits and Test Equivalence. Syntax TST{cond} Rn, Operand2 TEQ{cond} Rn, Operand2 Where: •... -
Page 100: Uadd16 And Uadd8
The STM32 Cortex-M4 instruction set PM0214 3.5.16 UADD16 and UADD8 Unsigned Add 16 and Unsigned Add 8 Syntax op{cond}{Rd,} Rn, Rm Where: • op is one of the following: UADD16: Performs two 16-bit unsigned integer additions. UADD8: Performs four 8-bit unsigned integer additions. •... -
Page 101: Uasx And Usax
PM0214 The STM32 Cortex-M4 instruction set 3.5.17 UASX and USAX Add and Subtract with Exchange and Subtract and Add with Exchange. Syntax op{cond} {Rd}, Rn, Rm Where: • op is one of: UASX: Add and subtract with exchange. USAX: Subtract and add with exchange. •... -
Page 102: Uhadd16 And Uhadd8
The STM32 Cortex-M4 instruction set PM0214 ; writes to top halfword of R7. 3.5.18 UHADD16 and UHADD8 Unsigned Halving Add 16 and Unsigned Halving Add 8 Syntax op{cond}{Rd,} Rn, Rm Where: • op is any of the following: UHADD16: Unsigned halving add 16. UHADD8: Unsigned halving add 8. -
Page 103: Uhasx And Uhsax
PM0214 The STM32 Cortex-M4 instruction set 3.5.19 UHASX and UHSAX Unsigned Halving Add and Subtract with Exchange and Unsigned Halving Subtract and Add with Exchange. Syntax op{cond} {Rd}, Rn, Rm Where: • op is one of the following: UHASX: Add and subtract with exchange and halving. UHSAX: Subtract and add with exchange and halving. -
Page 104: Uhsub16 And Uhsub8
The STM32 Cortex-M4 instruction set PM0214 UHSAX R0, R3, R5 ; Subtracts bottom halfword of R5 from top halfword of ; R3 and writes halved result to top halfword of R0 ; Adds top halfword of R5 to bottom halfword of R3 and ;... -
Page 105: Sel
PM0214 The STM32 Cortex-M4 instruction set UHSUB8 R4, R0, R5 ; Subtracts bytes of R5 from corresponding byte in R0 and ; writes halved result to corresponding byte in R4. 3.5.21 Select bytes. Selects each byte of its result from either its first operand or its second operand, according to the values of the GE flags. -
Page 106: Usad8
The STM32 Cortex-M4 instruction set PM0214 3.5.22 USAD8 Unsigned Sum of Absolute Differences Syntax USAD8{cond}{Rd,} Rn, Rm Where: • ‘cond’ is an optional condition code (see Conditional execution on page 65). • ‘Rd’ is the destination register. • ‘Rn’ is the first operand register. •... -
Page 107: Usada8
PM0214 The STM32 Cortex-M4 instruction set 3.5.23 USADA8 Unsigned Sum of Absolute Differences and Accumulate Syntax USADA8{cond}{Rd,} Rn, Rm, Ra Where: • ‘cond’ is an optional condition code (see Conditional execution on page 65). • ‘Rd’ is the destination register. •... -
Page 108: Usub16 And Usub8
The STM32 Cortex-M4 instruction set PM0214 3.5.24 USUB16 and USUB8 Unsigned Subtract 16 and Unsigned Subtract 8 Syntax op{cond}{Rd,} Rn, Rm Where: • op is any of: USUB16: Unsigned Subtract 16. USUB8: Unsigned Subtract 8. • ‘cond’ is an optional condition code (see Conditional execution on page •... -
Page 109: Multiply And Divide Instructions
PM0214 The STM32 Cortex-M4 instruction set Multiply and divide instructions Table 29 shows the multiply and divide instructions. Table 29. Multiply and divide instructions Mnemonic Brief description Multiply with Accumulate, 32-bit result MUL, MLA, and MLS on page 110 Multiply and Subtract, 32-bit result MUL, MLA, and MLS on page 110 Multiply, 32-bit result MUL, MLA, and MLS on page 110... -
Page 110: Mul, Mla, And Mls
The STM32 Cortex-M4 instruction set PM0214 3.6.1 MUL, MLA, and MLS Multiply, Multiply with Accumulate, and Multiply with Subtract, using 32-bit operands, and producing a 32-bit result. Syntax MUL{S}{cond} {Rd,} Rn, Rm ; Multiply MLA{cond} Rd, Rn, Rm, Ra ; Multiply with accumulate MLS{cond} Rd, Rn, Rm, Ra ;... -
Page 111: Umull, Umaal And Umlal
PM0214 The STM32 Cortex-M4 instruction set 3.6.2 UMULL, UMAAL and UMLAL Unsigned Long Multiply, with Optional Accumulate, 32-bit operands, producing a 64-bit result. Syntax op{cond} RdLo, RdHi, Rn, Rm Where: • ‘op’ is one of the following: UMULL: Unsigned long multiply. UMAAL: Unsigned long multiply, with accumulate accumulate. -
Page 112: Smla And Smlaw
The STM32 Cortex-M4 instruction set PM0214 ; top 32 bits to R6, and the bottom 32 bits to R3 UMLAL R2, R1, R3, R5 ; Multiplies R5 and R3, adds R1:R2, writes to R1:R2. 3.6.3 SMLA and SMLAW Signed Multiply Accumulate (halfwords). Syntax op{XY}{cond} Rd, Rn, Rm op{Y}{cond} Rd, Rn, Rm, Ra... - Page 113 PM0214 The STM32 Cortex-M4 instruction set Condition flags If an overflow is detected, the Q flag is set. Examples SMLABB R5, R6, R4, R1 ; Multiplies bottom halfwords of R6 and R4, adds ; R1 and writes to R5 SMLATB R5, R6, R4, R1 ;...
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Page 114: Smlad
The STM32 Cortex-M4 instruction set PM0214 3.6.4 SMLAD Signed Multiply Accumulate Long Dual Syntax op{X}{cond} Rd, Rn, Rm, Ra Where: • op is one of the following: SMLAD: Signed multiply accumulate dual. SMLADX: Signed multiply accumulate dual reverse. X specifies which halfword of the source register Rn is used as the multiply operand. -
Page 115: Smlal And Smlald
PM0214 The STM32 Cortex-M4 instruction set 3.6.5 SMLAL and SMLALD Signed Multiply Accumulate Long, Signed Multiply Accumulate Long (halfwords) and Signed Multiply Accumulate Long Dual. Syntax op{cond} RdLo, RdHi, Rn, Rm op{XY}{cond} RdLo, RdHi, Rn, Rm op{X}{cond} RdLo, RdHi, Rn, Rm Where: •... - Page 116 The STM32 Cortex-M4 instruction set PM0214 The SMLALD and SMLALDX instructions interpret the values from Rn and Rm as four halfword two’s complement signed 16-bit integers. These instructions: • If X is not present, multiply the top signed halfword value of Rn with the top signed halfword of Rm and the bottom signed halfword values of Rn with the bottom signed halfword of Rm.
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Page 117: Smlsd And Smlsld
PM0214 The STM32 Cortex-M4 instruction set 3.6.6 SMLSD and SMLSLD Signed Multiply Subtract Dual and Signed Multiply Subtract Long Dual Syntax op{X}{cond} Rd, Rn, Rm, Ra Where: • op is one of: SMLSD: Signed multiply subtract dual. SMLSDX: Signed multiply subtract dual reversed SMLSLD: Signed multiply subtract long dual. - Page 118 The STM32 Cortex-M4 instruction set PM0214 For the Thumb instruction set, these instructions do not affect the condition code flags. Examples SMLS R0, R4, R5, R6 ; Multiplies bottom halfword of R4 with bottom ; halfword of R5, multiplies top halfword of R4 ;...
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Page 119: Smmla And Smmls
PM0214 The STM32 Cortex-M4 instruction set 3.6.7 SMMLA and SMMLS Signed Most Significant Word Multiply Accumulate and Signed Most Significant Word Multiply Subtract. Syntax op{R}{cond} Rd, Rn, Rm, Ra Where: • op is one of the following: SMMLA: Signed most significant word multiply accumulate. SMMLS: Signed most significant word multiply subtract. -
Page 120: Smmul
The STM32 Cortex-M4 instruction set PM0214 SMMLS R4, R5, R3, R8 ; Multiplies R5 and R3, extracts top 32 bits, ; subtracts R8, truncates and writes to R4. 3.6.8 SMMUL Signed most significant word multiply Syntax op{R}{cond} Rd, Rn, Rm Where: •... -
Page 121: Smuad And Smusd
PM0214 The STM32 Cortex-M4 instruction set 3.6.9 SMUAD and SMUSD Signed Dual Multiply Add and Signed Dual Multiply Subtract Syntax op{X}{cond} Rd, Rn, Rm Where: • op is one of: SMUAD: Signed dual multiply add. SMUADX: Signed dual multiply add reversed. SMUSD: Signed dual multiply subtract. -
Page 122: Smul And Smulw
The STM32 Cortex-M4 instruction set PM0214 SMUSD R3, R6, R2 ; Multiplies bottom halfword of R4 with bottom halfword ; of R6, subtracts multiplication of top halfword of R6 ; with top halfword of R3, writes to R3 SMUSDX R4, R5, R3 ; Multiplies bottom halfword of R5 with top halfword of ;... -
Page 123: Umull, Umlal, Smull, And Smlal
PM0214 The STM32 Cortex-M4 instruction set SMULBB R0, R4, R5 ; Multiplies the bottom halfword of R4 with the bottom ; halfword of R5, multiplies results and writes to R0 SMULTT R0, R4, R5 ; Multiplies the top halfword of R4 with the top ;... -
Page 124: Sdiv And Udiv
The STM32 Cortex-M4 instruction set PM0214 Restrictions In these instructions: • Do not use either SP or PC • RdHi and RdLo must be different registers. Condition flags These instructions do not affect the condition code flags. Examples UMULL R0, R4, R5, R6 ;... -
Page 125: Saturating Instructions
PM0214 The STM32 Cortex-M4 instruction set Saturating instructions This section describes the saturating instructions. Table 30. Saturating instructions Mnemonic Brief description SSAT Signed Saturate SSAT and USAT on page 126 SSAT16 Signed Saturate Halfword SSAT16 and USAT16 on page 127 USAT Unsigned Saturate SSAT and USAT on page 126... -
Page 126: Ssat And Usat
The STM32 Cortex-M4 instruction set PM0214 3.7.1 SSAT and USAT Signed Saturate and Unsigned Saturate to any bit position, with optional shift before saturating. Syntax op{cond} Rd, #n, Rm {, shift #s} Where: • op’ is one of: SSAT: Saturates a signed value to a signed range. USAT: Saturates a signed value to an unsigned range. -
Page 127: Ssat16 And Usat16
PM0214 The STM32 Cortex-M4 instruction set 3.7.2 SSAT16 and USAT16 Signed Saturate and Unsigned Saturate to any bit position for two halfwords. Syntax op{cond} Rd, #n, Rm Where: • op’ is one of: SSAT16 Saturates a signed halfword value to a signed range. USAT16 Saturates a signed halfword value to an unsigned range. -
Page 128: Qadd And Qsub
The STM32 Cortex-M4 instruction set PM0214 3.7.3 QADD and QSUB Saturating Add and Saturating Subtract, signed. Syntax op{cond} {Rd}, Rn, Rm op{cond} {Rd}, Rn, Rm Where: • op’ is one of: QADD: Saturating 32-bit add. QADD8: Saturating four 8-bit integer additions. QADD16: Saturating two 16-bit integer additions. -
Page 129: Qasx And Qsax
PM0214 The STM32 Cortex-M4 instruction set ; of R2, saturates to 16 bits, writes to corresponding ; halfword of R4 QSUB8 R4, R2, R5 ; Subtracts bytes of R5 from the corresponding byte in R2 ; saturates to 8 bits, writes to corresponding byte ofR4. 3.7.4 QASX and QSAX Saturating Add and Subtract with Exchange and Saturating Subtract and Add with... -
Page 130: Qdadd And Qdsub
The STM32 Cortex-M4 instruction set PM0214 ; Subtracts top highword of R2 from bottom halfword of ; R4, saturates to 16 bits and writes to bottom halfword ; of R7 QSAX R0, R3, R5 ; Subtracts bottom halfword of R5 from top halfword of ;... -
Page 131: Uqasx And Uqsax
PM0214 The STM32 Cortex-M4 instruction set ; from R5, saturates to 32 bits, writes to R0. 3.7.6 UQASX and UQSAX Saturating Add and Subtract with Exchange and Saturating Subtract and Add with Exchange, unsigned. Syntax op{cond} {Rd}, Rm, Rn Where: •... -
Page 132: Uqadd And Uqsub
The STM32 Cortex-M4 instruction set PM0214 ; R4, saturates to 16 bits, writes to bottom halfword of R7 UQSAX R0, R3, R5 ; Subtracts bottom halfword of R5 from top halfword of ; R3, saturates to 16 bits, writes to top halfword of R0 ;... - Page 133 PM0214 The STM32 Cortex-M4 instruction set Restrictions Do not use SP and do not use PC. Condition flags These instructions do not affect the condition code flags. Examples UQADD16 R7, R4, R2; Adds halfwords in R4 to corresponding halfword in R2, ;...
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Page 134: Packing And Unpacking Instructions
The STM32 Cortex-M4 instruction set PM0214 Packing and unpacking instructions Table 31 shows the instructions that operate on packing and unpacking data: Table 31. Packing and unpacking instructions Mnemonic Brief description Pack Halfword PKHBT and PKHTB on page 135 SXTAB Extend 8 bits to 32 and add SXTA and UXTA on page 137 SXTAB16... -
Page 135: Pkhbt And Pkhtb
PM0214 The STM32 Cortex-M4 instruction set 3.8.1 PKHBT and PKHTB Pack Halfword Syntax op{cond} {Rd}, Rn, Rm {, LSL #imm} op{cond} {Rd}, Rn, Rm {, ASR #imm} Where: • op’ is one of: PKHBT Pack Halfword, bottom and top with shift. PKHTB Pack Halfword, top and bottom with shift. -
Page 136: Sxt And Uxt
The STM32 Cortex-M4 instruction set PM0214 3.8.2 SXT and UXT Sign extend and Zero extend. Syntax op{cond} {Rd,} Rm {, ROR #n} op{cond} {Rd}, Rm {, ROR #n} Where: • op’ is one of: SXTB Sign extends an 8-bit value to a 32-bit value. SXTH Sign extends a 16-bit value to a 32-bit value. -
Page 137: Sxta And Uxta
PM0214 The STM32 Cortex-M4 instruction set Examples SXTH R4, R6, ROR #16 ; Rotates R6 right by 16 bits, obtains bottom halfword ; of result, sign extends to 32 bits and writes to R4 UXTB R3, R10 ; Extracts lowest byte of value in R10, zero extends, and ;... -
Page 138: Bitfield Instructions
The STM32 Cortex-M4 instruction set PM0214 Restrictions Do not use SP and do not use PC. Condition flags These instructions do not affect the flags. Examples SXTAH R4, R8, R6, ROR #16 ; Rotates R6 right by 16 bits, obtains bottom ;... -
Page 139: Bfc And Bfi
PM0214 The STM32 Cortex-M4 instruction set 3.9.1 BFC and BFI Bit Field Clear and Bit Field Insert. Syntax BFC{cond} Rd, #lsb, #width BFI{cond} Rd, Rn, #lsb, #width Where: • ‘cond’ is an optional condition code, see Conditional execution on page •... -
Page 140: Sbfx And Ubfx
The STM32 Cortex-M4 instruction set PM0214 3.9.2 SBFX and UBFX Signed Bit Field Extract and Unsigned Bit Field Extract. Syntax SBFX{cond} Rd, Rn, #lsb, #width UBFX{cond} Rd, Rn, #lsb, #width Where: • ‘cond’ is an optional condition code, see Conditional execution on page •... -
Page 141: Sxt And Uxt
PM0214 The STM32 Cortex-M4 instruction set 3.9.3 SXT and UXT Sign extend and Zero extend. Syntax SXTextend{cond} {Rd,} Rm {, ROR #n} UXTextend{cond} {Rd}, Rm {, ROR #n} Where: • ‘extend’ is one of: B: Extends an 8-bit value to a 32-bit value. H: Extends a 16-bit value to a 32-bit value. -
Page 142: Branch And Control Instructions
The STM32 Cortex-M4 instruction set PM0214 3.9.4 Branch and control instructions Table 33 shows the branch and control instructions: Table 33. Branch and control instructions Mnemonic Brief description Branch B, BL, BX, and BLX on page 142 Branch with Link B, BL, BX, and BLX on page 142 Branch indirect with Link B, BL, BX, and BLX on page 142... -
Page 143: Table 34. Branch Ranges
PM0214 The STM32 Cortex-M4 instruction set B cond label is the only conditional instruction that can be either inside or outside an IT block. All other branch instructions must be conditional inside an IT block, and must be unconditional outside the IT block, see IT on page 145. -
Page 144: Cbz And Cbnz
The STM32 Cortex-M4 instruction set PM0214 ; Branch with link and exchange (Call) to a address stored ; in R0 3.9.6 CBZ and CBNZ Compare and Branch on Zero, Compare and Branch on Non-Zero. Syntax CBZ Rn, label CBNZ Rn, label Where: •... - Page 145 PM0214 The STM32 Cortex-M4 instruction set 3.9.7 If-Then condition instruction. Syntax IT{x{y{z}}} cond Where: • ‘x’ specifies the condition switch for the second instruction in the IT block. • ‘y’ specifies the condition switch for the third instruction in the IT block. •...
- Page 146 The STM32 Cortex-M4 instruction set PM0214 Other restrictions when using an IT block are: • a branch or any instruction that modifies the PC must either be outside an IT block or must be the last instruction inside the IT block. These are: –...
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Page 147: Tbb And Tbh
PM0214 The STM32 Cortex-M4 instruction set 3.9.8 TBB and TBH Table Branch Byte and Table Branch Halfword. Syntax TBB [Rn, Rm] TBH [Rn, Rm, LSL #1] Where: • ‘Rn’ is the register containing the address of the table of branch lengths. If Rn is PC, then the address of the table is the address of the byte immediately following the TBB or TBH instruction. - Page 148 The STM32 Cortex-M4 instruction set PM0214 BranchTable_H ((CaseA - BranchTable_H)/2) ; CaseA offset calculation ((CaseB - BranchTable_H)/2) ; CaseB offset calculation ((CaseC - BranchTable_H)/2) ; CaseC offset calculation CaseA ; an instruction sequence follows CaseB ; an instruction sequence follows CaseC ;...
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Page 149: Floating-Point Instructions
PM0214 The STM32 Cortex-M4 instruction set 3.10 Floating-point instructions These instructions are only available if the FPU is included, and enabled, in the system. See Enabling the FPU on page 257 for information about enabling the floating-point unit. Table 35. Floating-point instructions Mnemonic Brief description VABS... - Page 150 The STM32 Cortex-M4 instruction set PM0214 Table 35. Floating-point instructions Mnemonic Brief description Move to floating-point System Register from Arm VMSR VMSR on page 170 Core register VMUL Multiply floating-point VMUL on page 171 VNEG Floating-point negate VNEG on page 172 VNMLA, VNMLS, VNMUL on VNMLA Floating-point multiply and add...
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Page 151: Vabs
PM0214 The STM32 Cortex-M4 instruction set 3.10.1 VABS Floating-point Absolute. Syntax VABS{cond}.F32 Sd, Sm Where: • ‘cond’ is an optional condition code, see Conditional execution on page • ‘Sd, Sm’ are the destination floating-point value and the operand floating-point value. Operation This instruction: Takes the absolute value of the operand floating-point register. -
Page 152: Vadd
The STM32 Cortex-M4 instruction set PM0214 3.10.2 VADD Floating-point Add Syntax VADD{cond}.F32 {Sd,} Sn, Sm Where: • ‘cond’ is an optional condition code, see Conditional execution on page • ‘Sd’ is the destination floating-point value • ‘Sn, Sm’ are the operand floating-point values. Operation This instruction: Adds the values in the two floating-point operand registers. -
Page 153: Vcmp, Vcmpe
PM0214 The STM32 Cortex-M4 instruction set 3.10.3 VCMP, VCMPE Compares two floating-point registers, or one floating-point register and zero. Syntax VCMP{E}{cond}.F32 Sd, Sm VCMP{E}{cond}.F32 Sd, #0.0 Where: • ‘cond’ is an optional condition code, see Conditional execution on page • ‘E’... -
Page 154: Vcvt, Vcvtr Between Floating-Point And Integer
The STM32 Cortex-M4 instruction set PM0214 3.10.4 VCVT, VCVTR between floating-point and integer Converts a value in a register from floating-point to a 32-bit integer. Syntax VCVT{R}{cond}.Tm.F32 Sd, Sm VCVT{cond}.F32.Tm Sd, Sm Where: • ‘R’ . If R is specified, the operation uses the rounding mode specified by the FPSCR. If R is omitted. -
Page 155: Vcvt Between Floating-Point And Fixed-Point
PM0214 The STM32 Cortex-M4 instruction set 3.10.5 VCVT between floating-point and fixed-point Converts a value in a register from floating-point to and from fixed-point. Syntax VCVT{cond}.Td.F32 Sd, Sd, #fbits VCVT{cond}.F32.Td Sd, Sd, #fbits Where: • ‘cond’ is an optional condition code, see Conditional execution on page •... -
Page 156: Vcvtb, Vcvtt
The STM32 Cortex-M4 instruction set PM0214 3.10.6 VCVTB, VCVTT Converts between a half-precision value and a single-precision value. Syntax VCVT{y}{cond}.F32.F16 Sd, Sm VCVT{y}{cond}.F16.F32 Sd, Sm Where: • ‘y’ Specifies which half of the operand register Sm or destination register Sd is used for the operand or destination: If y is B, then the bottom half, bits [15:0], of Sm or Sd is used. -
Page 157: Vdiv
PM0214 The STM32 Cortex-M4 instruction set 3.10.7 VDIV Divides floating-point values. Syntax VDIV{cond}.F32 {Sd,} Sn, Sm Where: • ‘cond’ is an optional condition code, see Conditional execution on page • ‘Sd’ is the destination register • ‘Sn, Sm’ are the operand registers. Operation This instruction: Divides one floating-point value by another floating-point value. -
Page 158: Vfma, Vfms
The STM32 Cortex-M4 instruction set PM0214 3.10.8 VFMA, VFMS Floating-point Fused Multiply Accumulate and Subtract. Syntax VFMA{cond}.F32 {Sd,} Sn, Sm VFMS{cond}.F32 {Sd,} Sn, Sm Where: • ‘cond’ is an optional condition code, see Conditional execution on page • ‘Sd’ is the destination register •... -
Page 159: Vfnma, Vfnms
PM0214 The STM32 Cortex-M4 instruction set 3.10.9 VFNMA, VFNMS Floating-point Fused Negate Multiply Accumulate and Subtract. Syntax VFNMA{cond}.F32 {Sd,} Sn, Sm VFNMS{cond}.F32 {Sd,} Sn, Sm Where: • ‘cond’ is an optional condition code, see Conditional execution on page • ‘Sd’ is the destination register •... -
Page 160: Vldm
The STM32 Cortex-M4 instruction set PM0214 3.10.10 VLDM Floating-point Load Multiple Syntax VLDM{mode}{cond}{.size} Rn{!}, list Where: • ‘mode’ is the addressing mode: IA: Increment After. The consecutive addresses start at the address specified in Rn. DB: Decrement Before. The consecutive addresses end just before the address specified in Rn. -
Page 161: Vldr
PM0214 The STM32 Cortex-M4 instruction set 3.10.11 VLDR Loads a single extension register from memory Syntax VLDR{cond}{.64} Dd, [Rn{#imm}] VLDR{cond}{.64} Dd, label VLDR{cond}{.64} Dd, [PC, #imm}] VLDR{cond}{.32} Sd, [Rn {, #imm}] VLDR{cond}{.32} Sd, label VLDR{cond}{.32} Sd, [PC, #imm] Where: • ‘cond’... -
Page 162: Vlma, Vlms
The STM32 Cortex-M4 instruction set PM0214 3.10.12 VLMA, VLMS Multiplies two floating-point values, and accumulates or subtracts the results. Syntax VLMA{cond}.F32 Sd, Sn, Sm VLMS{cond}.F32 Sd, Sn, Sm Where: • ‘cond’ is an optional condition code, see Conditional execution on page •... -
Page 163: Vmov Immediate
PM0214 The STM32 Cortex-M4 instruction set 3.10.13 VMOV immediate Move floating-point immediate Syntax VMOV{cond}.F32 Sd, #imm Where: • ‘cond’ is an optional condition code, see Conditional execution on page • ‘Sd’ is the branch destination • ‘imm’ is a floating-point constant. Operation This instruction copies a constant value to a floating-point register. -
Page 164: Vmov Register
The STM32 Cortex-M4 instruction set PM0214 3.10.14 VMOV register Copies the contents of one register to another. Syntax VMOV{cond}.F64 Dd, Dm VMOV{cond}.F32 Sd, Sm Where: • ‘cond’ is an optional condition code, see Conditional execution on page • ‘Dd’ is the destination register, for a doubleword operation. •... -
Page 165: Vmov Scalar To Arm Core Register
PM0214 The STM32 Cortex-M4 instruction set 3.10.15 VMOV scalar to Arm core register Transfers one word of a doubleword floating-point register to an Arm core register. Syntax VMOV{cond} Rt, Dn[x] Where: • ‘cond’ is an optional condition code, see Conditional execution on page •... -
Page 166: Vmov Arm Core Register To Single Precision
The STM32 Cortex-M4 instruction set PM0214 3.10.16 VMOV Arm core register to single precision Transfers a single-precision register to and from an Arm core register. Syntax VMOV{cond} Sn, Rt VMOV{cond} Rt, Sn Where: • ‘cond’ is an optional condition code, see Conditional execution on page •... -
Page 167: Vmov Two Arm Core Registers To Two Single Precision
PM0214 The STM32 Cortex-M4 instruction set 3.10.17 VMOV two Arm core registers to two single precision Transfers two consecutively numbered single-precision registers to and from two Arm core registers. Syntax VMOV{cond} Sm, Sm1, Rt, Rt2 VMOV{cond} Rt, Rt2, Sm, Sm Where: •... -
Page 168: Vmov Arm Core Register To Scalar
The STM32 Cortex-M4 instruction set PM0214 3.10.18 VMOV Arm Core register to scalar Transfers one word to a floating-point register from an Arm core register. Syntax VMOV{cond}{.32} Dd[x], Rt Where: • ‘cond’ is an optional condition code, see Conditional execution on page •... -
Page 169: Vmrs
PM0214 The STM32 Cortex-M4 instruction set 3.10.19 VMRS Move to Arm Core register from floating-point System Register. Syntax VMRS{cond} Rt, FPSCR VMRS{cond} APSR_nzcv, FPSCR Where: • ‘cond’ is an optional condition code, see Conditional execution on page • ‘Rt’ is the destination Arm core register. This register can be R0-R14. •... -
Page 170: Vmsr
The STM32 Cortex-M4 instruction set PM0214 3.10.20 VMSR Move to floating-point System Register from Arm Core register. Syntax VMSR{cond} FPSCR, Rt Where: • ‘cond’ is an optional condition code, see Conditional execution on page • ‘Rt’ is the general-purpose register to be transferred to the FPSCR. Operation This instruction moves the value of a general-purpose register to the FPSCR. -
Page 171: Vmul
PM0214 The STM32 Cortex-M4 instruction set 3.10.21 VMUL Floating-point Multiply. Syntax VMUL{cond}.F32 {Sd,} Sn, Sm Where: • ‘cond’ is an optional condition code, see Conditional execution on page • ‘Sd’ is the destination floating-point value • ‘Sn, Sm’ are the operand floating-point values. Operation This instruction: Multiplies two floating-point values. -
Page 172: Vneg
The STM32 Cortex-M4 instruction set PM0214 3.10.22 VNEG Floating-point Negate. Syntax VNEG{cond}.F32 Sd, Sm Where: • ‘cond’ is an optional condition code, see Conditional execution on page • ‘Sd’ is the destination floating-point value • ‘Sm’ is the operand floating-point value. Operation This instruction: Negates a floating-point value. -
Page 173: Vnmla, Vnmls, Vnmul
PM0214 The STM32 Cortex-M4 instruction set 3.10.23 VNMLA, VNMLS, VNMUL Floating-point multiply with negation followed by add or subtract. Syntax VNMLA{cond}.F32 Sd, Sn, Sm VNMLS{cond}.F32 Sd, Sn, Sm VNMUL{cond}.F32 {Sd,} Sn, Sm Where: • ‘cond’ is an optional condition code, see Conditional execution on page •... -
Page 174: Vpop
The STM32 Cortex-M4 instruction set PM0214 3.10.24 VPOP Floating-point extension register Pop. Syntax VPOP{cond}{.size} list Where: • ‘cond’ is an optional condition code, see Conditional execution on page • ‘size’ is an optional data size specifier. If present, it must be equal to the size in bits, 32 or 64, of the registers in list. -
Page 175: Vpush
PM0214 The STM32 Cortex-M4 instruction set 3.10.25 VPUSH Floating-point extension register Push. Syntax VPUSH{cond}{.size} list Where: • ‘cond’ is an optional condition code, see Conditional execution on page • ‘size’ is an optional data size specifier. If present, it must be equal to the size in bits, 32 or 64, of the registers in list. -
Page 176: Vsqrt
The STM32 Cortex-M4 instruction set PM0214 3.10.26 VSQRT Floating-point Square Root. Syntax VSQRT{cond}.F32 Sd, Sm Where: • ‘cond’ is an optional condition code, see Conditional execution on page • ‘Sd’ is the destination floating-point value • ‘Sm’ is the operand floating-point value. Operation This instruction: Calculates the square root of the value in a floating-point register. -
Page 177: Vstm
PM0214 The STM32 Cortex-M4 instruction set 3.10.27 VSTM Floating-point Store Multiple. Syntax VSTM{mode}{cond}{.size} Rn{!}, list Where: • ‘mode’ is the addressing mode: IA Increment After. The consecutive addresses start at the address specified in Rn. This is the default and can be omitted. DB Decrement Before. -
Page 178: Vstr
The STM32 Cortex-M4 instruction set PM0214 3.10.28 VSTR Floating-point Store. Syntax VSTR{cond}{.32} Sd, [Rn{, #imm}] VSTR{cond}{.64} Dd, [Rn{, #imm}] Where: • ‘cond’ is an optional condition code, see Conditional execution on page • ‘32, 64’ are the optional data size specifiers. •... -
Page 179: Vsub
PM0214 The STM32 Cortex-M4 instruction set 3.10.29 VSUB Floating-point Subtract. Syntax VSUB{cond}.F32 {Sd,} Sn, Sm Where: • ‘cond’ is an optional condition code, see Conditional execution on page • ‘Sd’ is the destination floating-point value • ‘Sn, Sm’ are the operand floating-point values. Operation This instruction: Subtracts one floating-point value from another floating-point value. -
Page 180: Miscellaneous Instructions
The STM32 Cortex-M4 instruction set PM0214 3.11 Miscellaneous instructions Table 36 shows the remaining Cortex-M4 instructions: Table 36. Miscellaneous instructions Mnemonic Brief description BKPT Breakpoint BKPT on page 181 CPSID Change Processor State, Disable Interrupts CPS on page 182 CPSIE Change Processor State, Enable Interrupts CPS on page 182 Data Memory Barrier... -
Page 181: Bkpt
PM0214 The STM32 Cortex-M4 instruction set 3.11.1 BKPT Breakpoint. Syntax BKPT #imm Where: • ‘imm’ is an expression evaluating to an integer in the range 0-255 (8-bit value). Operation The BKPT instruction causes the processor to enter Debug state. Debug tools can use this to investigate system state when the instruction at a particular address is reached. -
Page 182: Cps
The STM32 Cortex-M4 instruction set PM0214 3.11.2 Change processor state. Syntax CPSeffect iflags Where: • ‘effect’ is one of: IE: Clears the special purpose register. ID: Sets the special purpose register. • ‘iflags’ is a sequence of one or more flags: i: Set or clear PRIMASK. -
Page 183: Dmb
PM0214 The STM32 Cortex-M4 instruction set 3.11.3 Data memory barrier. Syntax DMB{cond} Where: ‘cond’ is an optional condition code, see Conditional execution on page Operation DMB acts as a data memory barrier. It ensures that all explicit memory accesses that appear, in program order, before the DMB instruction are completed before any explicit memory accesses that appear, in program order, after the DMB instruction. -
Page 184: Dsb
The STM32 Cortex-M4 instruction set PM0214 3.11.4 Data synchronization barrier. Syntax DSB{cond} Where: ‘cond’ is an optional condition code, see Conditional execution on page Operation DSB acts as a special data synchronization memory barrier. Instructions that come after the DSB, in program order, do not execute until the DSB instruction completes. The DSB instruction completes when all explicit memory accesses before it complete. -
Page 185: Isb
PM0214 The STM32 Cortex-M4 instruction set 3.11.5 Instruction synchronization barrier. Syntax ISB{cond} Where: ‘cond’ is an optional condition code, see Conditional execution on page Operation ISB acts as an instruction synchronization barrier. It flushes the pipeline of the processor, so that all instructions following the ISB are fetched from cache or memory again, after the ISB instruction is completed. -
Page 186: Mrs
The STM32 Cortex-M4 instruction set PM0214 3.11.6 Move the contents of a special register to a general-purpose register. Syntax MRS{cond} Rd, spec_reg Where: • ‘cond’ is an optional condition code, see Conditional execution on page • ‘Rd’ is the destination register. •... -
Page 187: Msr
PM0214 The STM32 Cortex-M4 instruction set 3.11.7 Move the contents of a general-purpose register into the specified special register. Syntax MSR{cond} spec_reg, Rn Where: • ‘cond’ is an optional condition code, see Conditional execution on page • ‘Rn’ is the source register. •... -
Page 188: Nop
The STM32 Cortex-M4 instruction set PM0214 3.11.8 No Operation. Syntax NOP{cond} Where: • ‘cond’ is an optional condition code, see Conditional execution on page Operation NOP does nothing. NOP is not necessarily a time-consuming NOP. The processor might remove it from the pipeline before it reaches the execution stage. Use NOP for padding, for example to place the following instruction on a 64-bit boundary. -
Page 189: Sev
PM0214 The STM32 Cortex-M4 instruction set 3.11.9 Send Event. Syntax SEV{cond} Where: • ‘cond’ is an optional condition code, see Conditional execution on page Operation SEV is a hint instruction that causes an event to be signaled to all processors within a multiprocessor system. -
Page 190: Svc
The STM32 Cortex-M4 instruction set PM0214 3.11.10 Supervisor Call. Syntax SVC{cond} #imm Where: • ‘cond’ is an optional condition code, see Conditional execution on page • ‘imm’ is an expression evaluating to an integer in the range 0-255 (8-bit value). Operation The SVC instruction causes the SVC exception. -
Page 191: Wfe
PM0214 The STM32 Cortex-M4 instruction set 3.11.11 Wait For Event. WFE is a hint instruction. Syntax WFE{cond} Where: ‘cond’ is an optional condition code, see Conditional execution on page Operation If the event register is 0, WFE suspends execution until one of the following events occurs: •... -
Page 192: Wfi
The STM32 Cortex-M4 instruction set PM0214 3.11.12 Wait for Interrupt. Syntax WFI{cond} Where: • ‘cond’ is an optional condition code, see Conditional execution on page Operation WFI is a hint instruction that suspends execution until one of the following events occurs: •... -
Page 193: Core Peripherals
PM0214 Core peripherals Core peripherals About the STM32 Cortex-M4 core peripherals The address map of the Private peripheral bus (PPB) is: Table 37. STM32 core peripheral register regions Address Core peripheral Description 0xE000E010-0xE000E01F System timer Table 55 on page 251 Nested vectored interrupt 0xE000E100-0xE000E4EF Table 49 on page 219... -
Page 194: Table 38. Memory Attributes Summary
Core peripherals PM0214 When memory regions overlap, a memory access is affected by the attributes of the region with the highest number. For example, the attributes for region 7 take precedence over the attributes of any region that overlaps region 7. The background region has the same memory access attributes as the default memory map, but is accessible from privileged software only. -
Page 195: Mpu Access Permission Attributes
PM0214 Core peripherals 4.2.1 MPU access permission attributes This section describes the MPU access permission attributes. The access permission bits, TEX, C, B, S, AP, and XN, of the MPU_RASR register, control access to the corresponding memory region. If an access is made to an area of memory without the required permissions, then the MPU generates a permission fault. -
Page 196: Mpu Mismatch
Core peripherals PM0214 Table 41 shows the AP encodings that define the access permissions for privileged and unprivileged software. Table 41. AP encoding Privileged Unprivileged AP[2:0] Description permissions permissions No access No access All accesses generate a permission fault No access Access from privileged software only Writes by unprivileged software generate a permission fault... - Page 197 PM0214 Core peripherals ; R3 = attributes ; R4 = address LDR R0,=MPU_RNR ; 0xE000ED98, MPU region number register STR R1, [R0, #0x0] ; Region Number BIC R2, R2, #1 ; Disable STRH R2, [R0, #0x8] ; Region Size and Enable STR R4, [R0, #0x4] ;...
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Page 198: Figure 18. Subregion Example
Core peripherals PM0214 ; R1 = address and region number in one ; R2 = size and attributes in one LDR R0, =MPU_RBAR ; 0xE000ED9C, MPU Region Base register STR R1, [R0, #0x0] ; Region base address and ; region number combined with VALID (bit 4) set to 1 STR R2, [R0, #0x4] ;... -
Page 199: Mpu Design Hints And Tips
PM0214 Core peripherals 4.2.4 MPU design hints and tips To avoid unexpected behavior, disable the interrupts before updating the attributes of a region that the interrupt handlers might access. Ensure software uses aligned accesses of the correct size to access MPU registers: •... -
Page 200: Mpu Type Register (Mpu_Typer)
Core peripherals PM0214 4.2.5 MPU type register (MPU_TYPER) Address offset: 0x00 Reset value: 0x0000 0800 Required privilege: Privileged The MPU_TYPER register indicates whether the MPU is present, and if so, how many regions it supports. Reserved IREGION[7:0] SEPA DREGION[7:0] Reserved RATE Bits 31:24 Reserved. -
Page 201: Mpu Control Register (Mpu_Ctrl)
PM0214 Core peripherals 4.2.6 MPU control register (MPU_CTRL) Address offset: 0x04 Reset value: 0x0000 0000 Required privilege: Privileged The MPU_CTRL register: • Enables the MPU • Enables the default memory map background region • Enables use of the MPU when in the hard fault, Non-maskable Interrupt (NMI), and FAULTMASK escalated handlers. -
Page 202: Mpu Region Number Register (Mpu_Rnr)
Core peripherals PM0214 Bits 31:3 Reserved, forced by hardware to 0. Bit 2 PRIVDEFENA: Enable priviliged software access to default memory map. 0: If the MPU is enabled, disables use of the default memory map. Any memory access to a location not covered by any enabled region causes a fault. -
Page 203: Mpu Region Base Address Register (Mpu_Rbar)
PM0214 Core peripherals 4.2.8 MPU region base address register (MPU_RBAR) Address offset: 0x0C Reset value: 0x0000 0000 Required privilege: Privileged The MPU_RBAR register defines the base address of the MPU region selected by the MPU_RNR register, and can update the value of the MPU_RNR register. Write to the MPU_RBAR register with the VALID bit set to 1 to change the current region number and update the MPU_RNR register. -
Page 204: Mpu Region Attribute And Size Register (Mpu_Rasr)
Core peripherals PM0214 4.2.9 MPU region attribute and size register (MPU_RASR) Address offset: 0x10 Reset value: 0x0000 0000 Required privilege: Privileged The MPU_RASR register defines the region size and memory attributes of the MPU region specified by the MPU_RNR, and enables that region and any subregions. MPU_RASR is accessible using word or halfword accesses: •... -
Page 205: Table 43. Example Size Field Values
PM0214 Core peripherals Bits 15:8 SRD: Subregion disable bits. For each bit in this field: 0: corresponding sub-region is enabled 1: corresponding sub-region is disabled Subregions on page 198 for more information. Region sizes of 128 bytes and less do not support subregions. When writing the attributes for such a region, write the SRD field as 0x00. -
Page 206: Mpu Register Map
Core peripherals PM0214 4.2.10 MPU register map Table 44. MPU register map and reset values Offset Register MPU_TYPER Reserved IREGION[7:0] DREGION[7:0] Reserved 0x00 Reset Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 MPU_CTRL Reserved 0x04... - Page 207 PM0214 Core peripherals Table 44. MPU register map and reset values (continued) Offset Register MPU_RBAR_A3 ADDR[31:N]... 0x1C Reset Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MPU_RASR_A3 AP[2:0] S C B...
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Page 208: Nested Vectored Interrupt Controller (Nvic)
Core peripherals PM0214 Nested vectored interrupt controller (NVIC) This section describes the Nested Vectored Interrupt Controller (NVIC) and the registers it uses. The NVIC supports: • Up to 240 interrupts • A programmable priority level of 0-15 for each interrupt. A higher level corresponds to a lower priority, so level 0 is the highest interrupt priority •... -
Page 209: Accessing The Cortex-M4 Nvic Registers Using Cmsis
PM0214 Core peripherals 4.3.1 Accessing the Cortex-M4 NVIC registers using CMSIS CMSIS functions enable software portability between different Cortex-M profile processors. To access the NVIC registers when using CMSIS, use the following functions: Table 46. CMSIS access NVIC functions CMSIS function Description void NVIC_EnableIRQ(IRQn_Type IRQn) Enables an interrupt or exception. -
Page 210: Interrupt Set-Enable Register X (Nvic_Iserx)
Core peripherals PM0214 4.3.2 Interrupt set-enable register x (NVIC_ISERx) Address offset: 0x100 + 0x04 * x, (x = 0 to 7) Reset value: 0x0000 0000 Required privilege: Privileged NVIC_ISER0 bits 0 to 31 are for interrupt 0 to 31, respectively NVIC_ISER1 bits 0 to 31 are for interrupt 32 to 63, respectively .. -
Page 211: Interrupt Clear-Enable Register X (Nvic_Icerx)
PM0214 Core peripherals 4.3.3 Interrupt clear-enable register x (NVIC_ICERx) Address offset: 0x180 + 0x04 * x, (x = 0 to 7) Reset value: 0x0000 0000 Required privilege: Privileged NVIC_ICER0 bits 0 to 31 are for interrupt 0 to 31, respectively NVIC_ICER1 bits 0 to 31 are for interrupt 32 to 63, respectively .. -
Page 212: Interrupt Set-Pending Register X (Nvic_Isprx)
Core peripherals PM0214 4.3.4 Interrupt set-pending register x (NVIC_ISPRx) Address offset: 0x200 + 0x04 * x, (x = 0 to 7) Reset value: 0x0000 0000 Required privilege: Privileged NVIC_ISPR0 bits 0 to 31 are for interrupt 0 to 31, respectively NVIC_ISPR1 bits 0 to 31 are for interrupt 32 to 63, respectively .. -
Page 213: Interrupt Clear-Pending Register X (Nvic_Icprx)
PM0214 Core peripherals 4.3.5 Interrupt clear-pending register x (NVIC_ICPRx) Address offset: 0x280 + 0x04 * x, (x = 0 to 7) Reset value: 0x0000 0000 Required privilege: Privileged NVIC_ICPR0 bits 0 to 31 are for interrupt 0 to 31, respectively NVIC_ICPR1 bits 0 to 31 are for interrupt 32 to 63, respectively .. -
Page 214: Interrupt Active Bit Register X (Nvic_Iabrx)
Core peripherals PM0214 4.3.6 Interrupt active bit register x (NVIC_IABRx) Address offset: 0x300 + 0x04 * x, (x = 0 to 7) Reset value: 0x0000 0000 Required privilege: Privileged NVIC_IABR0 bits 0 to 31 are for interrupt 0 to 31, respectively NVIC_IABR1 bits 0 to 31 are for interrupt 32 to 63, respectively .. -
Page 215: Interrupt Priority Register X (Nvic_Iprx)
PM0214 Core peripherals 4.3.7 Interrupt priority register x (NVIC_IPRx) Address offset: 0x400 + 0x04 * x, (x = 0 to 59) Reset value: 0x0000 0000 Required privilege: Privileged The NVIC_IPRx (x = 0 to 59) byte-accessible registers provide 8-bit priority fields IP[N] (N = 0 to 239) for each of the 240 interrupts. -
Page 216: Software Trigger Interrupt Register (Nvic_Stir)
Core peripherals PM0214 4.3.8 Software trigger interrupt register (NVIC_STIR) Address offset: 0xE00 Reset value: 0x0000 0000 Required privilege: When the USERSETMPEND bit in the SCR is set to 1, unprivileged software can access the STIR, see Section 4.4.6: System control register (SCR). -
Page 217: Level-Sensitive And Pulse Interrupts
PM0214 Core peripherals 4.3.9 Level-sensitive and pulse interrupts STM32 interrupts are both level-sensitive and pulse-sensitive. Pulse interrupts are also described as edge-triggered interrupts. A level-sensitive interrupt is held asserted until the peripheral deasserts the interrupt signal. Typically this happens because the ISR accesses the peripheral, causing it to clear the interrupt request. -
Page 218: Nvic Design Hints And Tips
Core peripherals PM0214 4.3.10 NVIC design hints and tips Ensure software uses correctly aligned register accesses. The processor does not support unaligned accesses to NVIC registers. See the individual register descriptions for the supported access sizes. An interrupt can enter pending state even it is disabled. Disabling an interrupt only prevents the processor from taking that interrupt. -
Page 219: Nvic Register Map
PM0214 Core peripherals 4.3.11 NVIC register map This table shows the NVIC register map and reset values. The base address of the main NVIC register block is 0xE000E100. The NVIC_STIR register is located in a separate block at 0xE000EF00. Table 49. NVIC register map and reset values Offset Register NVIC_ISER0... - Page 220 Core peripherals PM0214 Table 49. NVIC register map and reset values (continued) Offset Register NVIC_IABR1 ACTIVE[63:32] 0x304 Reset Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NVIC_IABR7 Reserved ACTIVE [239:224]...
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Page 221: System Control Block (Scb)
PM0214 Core peripherals System control block (SCB) The System control block (SCB) provides system implementation information, and system control. This includes configuration, control, and reporting of the system exceptions. Table 50. Summary of the system control block registers Required Address Name Type Reset value... -
Page 222: Auxiliary Control Register (Actlr)
Core peripherals PM0214 4.4.1 Auxiliary control register (ACTLR) Address offset: 0x00 (base adress = 0xE000 E008) Reset value: 0x0000 0000 Required privilege: Privileged By default this register is set to provide optimum performance from the Cortex-M4 processor, and does not normally require modification. The ACTLR register provides disable bits for the following processor functions: •... - Page 223 PM0214 Core peripherals DISFOLD Bit 2 Disables folding of IT instructions: 0: Enables IT instructions folding. 1: Disables IT instructions folding. In some situations, the processor can start executing the first instruction in an IT block while it is still executing the IT instruction. This behavior is called IT folding, and improves performance, However, IT folding can cause jitter in looping.
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Page 224: Cpuid Base Register (Cpuid)
Core peripherals PM0214 4.4.2 CPUID base register (CPUID) Address offset: 0x00 Reset value: 0x410F C241 Required privilege: Privileged The CPUID register contains the processor part number, version, and implementation information. Implementer Variant Constant PartNo Revision Bits 31:24 Implementer: Implementer code 0x41: Arm Bits 23:20 Variant: Variant number The r value in the rnpn product revision identifier... -
Page 225: Interrupt Control And State Register (Icsr)
PM0214 Core peripherals 4.4.3 Interrupt control and state register (ICSR) Address offset: 0x04 Reset value: 0x0000 0000 Required privilege: Privileged The ICSR: • Provides: – A set-pending bit for the Non-Maskable Interrupt (NMI) exception – Set-pending and clear-pending bits for the PendSV and SysTick exceptions •... - Page 226 Core peripherals PM0214 Bit 28 PENDSVSET: PendSV set-pending bit. Write: 0: No effect 1: Change PendSV exception state to pending. Read: 0: PendSV exception is not pending 1: PendSV exception is pending Writing 1 to this bit is the only way to set the PendSV exception state to pending. Bit 27 PENDSVCLR: PendSV clear-pending bit.
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Page 227: Vector Table Offset Register (Vtor)
PM0214 Core peripherals 4.4.4 Vector table offset register (VTOR) Address offset: 0x08 Reset value: 0x0000 0000 Required privilege: Privileged TBLOFF[29:16] Reserved TBLOFF[15:9] Reserved Bits 31:30 Reserved, must be kept cleared Bits 29:9 TBLOFF: Vector table base offset field. It contains bits [29:9] of the offset of the table base from memory address 0x00000000. When setting TBLOFF, you must align the offset to the number of exception entries in the vector table. -
Page 228: Application Interrupt And Reset Control Register (Aircr)
Core peripherals PM0214 4.4.5 Application interrupt and reset control register (AIRCR) Address offset: 0x0C Reset value: 0xFA05 0000 Required privilege: Privileged The AIRCR provides priority grouping control for the exception model, endian status for data accesses, and reset control of the system. To write to this register, you must write 0x5FA to the VECTKEY field, otherwise the processor ignores the write. -
Page 229: Table 51. Priority Grouping
PM0214 Core peripherals bits you might require more explanation here, and want to remove invalid rows from the table, and modify the entries in the number of columns. Table 51. Priority grouping Interrupt priority level value, PRI_N[7:4] Number of PRIGROUP Binary Group priority Subpriority... -
Page 230: System Control Register (Scr)
Core peripherals PM0214 4.4.6 System control register (SCR) Address offset: 0x10 Reset value: 0x0000 0000 Required privilege: Privileged The SCR controls features of entry to and exit from low power state. Reserved SLEEP SEVON SLEEP PEND DEEP Reserved Res. Res. EXIT Bits 31:5 Reserved, must be kept cleared Bit 4 SEVEONPEND Send Event on Pending bit... -
Page 231: Configuration And Control Register (Ccr)
PM0214 Core peripherals 4.4.7 Configuration and control register (CCR) Address offset: 0x14 Reset value: 0x0000 0200 Required privilege: Privileged The CCR controls entry to Thread mode and enables: • The handlers for NMI, hard fault and faults escalated by FAULTMASK to ignore bus faults •... - Page 232 Core peripherals PM0214 UNALIGN_ TRP Bit 3 Enables unaligned access traps: 0: Do not trap unaligned halfword and word accesses 1: Trap unaligned halfword and word accesses. If this bit is set to 1, an unaligned access generates a usage fault. Unaligned LDM, STM, LDRD, and STRD instructions always fault irrespective of whether UNALIGN_TRP is set to 1.
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Page 233: System Handler Priority Registers (Shprx)
PM0214 Core peripherals 4.4.8 System handler priority registers (SHPRx) The SHPR1-SHPR3 registers set the priority level, 0 to 255 of the exception handlers that have configurable priority. SHPR1-SHPR3 are byte accessible. The system fault handlers and the priority field and register for each handler are: Table 52. - Page 234 Core peripherals PM0214 PRI_11[7:4] PRI_11[3:0] Reserved Reserved Bits 31:24 PRI_11: Priority of system handler 11, SVCall Bits 23:0 Reserved, must be kept cleared System handler priority register 3 (SHPR3) Address: 0xE000 ED20 Reset value: 0x0000 0000 Required privilege: Privileged PRI_15[7:4] PRI_15[3:0] PRI_14[7:4] PRI_14[3:0]...
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Page 235: System Handler Control And State Register (Shcsr)
PM0214 Core peripherals 4.4.9 System handler control and state register (SHCSR) Address offset: 0x24 Reset value: 0x0000 0000 Required privilege: Privileged The SHCSR enables the system handlers, and indicates: • The pending status of the bus fault, memory management fault, and SVC exceptions •... - Page 236 Core peripherals PM0214 Bit 8 MONITORACT: Debug monitor active bit, reads as 1 if Debug monitor is active Bit 7 SVCALLACT: SVC call active bit, reads as 1 if SVC call is active Bits 6:4 Reserved, must be kept cleared Bit 3 USGFAULTACT: Usage fault exception active bit, reads as 1 if exception is active Reserved, must be kept cleared Bit 2...
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Page 237: Configurable Fault Status Register (Cfsr; Ufsr+Bfsr+Mmfsr)
PM0214 Core peripherals 4.4.10 Configurable fault status register (CFSR; UFSR+BFSR+MMFSR) Address offset: 0x28 Reset value: 0x0000 0000 Required privilege: Privileged The following subsections describe the subregisters that make up the CFSR: • Usage fault status register (UFSR) on page 238 •... -
Page 238: Usage Fault Status Register (Ufsr)
Core peripherals PM0214 4.4.11 Usage fault status register (UFSR) Bits 31:26 Reserved, must be kept cleared Bit 25 DIVBYZERO: Divide by zero usage fault. When the processor sets this bit to 1, the PC value stacked for the exception return points to the instruction that performed the divide by zero. Enable trapping of divide by zero by setting the DIV_0_TRP bit in the CCR to 1, see Configuration and control register (CCR) on page 231. -
Page 239: Bus Fault Status Register (Bfsr)
PM0214 Core peripherals 4.4.12 Bus fault status register (BFSR) Bit 15 BFARVALID: Bus Fault Address Register (BFAR) valid flag. The processor sets this bit to 1 after a bus fault where the address is known. Other faults can set this bit to 0, such as a memory management fault occurring later. -
Page 240: Memory Management Fault Address Register (Mmfsr)
Core peripherals PM0214 4.4.13 Memory management fault address register (MMFSR) Bit 7 MMARVALID: Memory Management Fault Address Register (MMAR) valid flag. If a memory management fault occurs and is escalated to a hard fault because of priority, the hard fault handler must set this bit to 0. -
Page 241: Hard Fault Status Register (Hfsr)
PM0214 Core peripherals 4.4.14 Hard fault status register (HFSR) Address offset: 0x2C Reset value: 0x0000 0000 Required privilege: Privileged The HFSR gives information about events that activate the hard fault handler. This register is read, write to clear. This means that bits in the register read normally, but writing 1 to any bit clears that bit to 0. -
Page 242: Memory Management Fault Address Register (Mmfar)
Core peripherals PM0214 4.4.15 Memory management fault address register (MMFAR) Address offset: 0x34 Reset value: undefined Required privilege: Privileged MMFAR[31:16] MMFAR[15:0] Bits 31:0 MMFAR: Memory management fault address When the MMARVALID bit of the MMFSR is set to 1, this field holds the address of the location that generated the memory management fault. -
Page 243: Auxiliary Fault Status Register (Afsr)
PM0214 Core peripherals 4.4.17 Auxiliary fault status register (AFSR) Address offset: 0x3C Reset value: undefined Required privilege: Privileged IMPDEF[31:16] IMPDEF[15:0] Bits 31:0 IMPDEF: Implementation defined. The AFSR contains additional system fault information. The bits map to the AUXFAULT input signals. This register is read, write to clear. -
Page 244: Scb Register Map
Core peripherals PM0214 4.4.19 SCB register map The table provides shows the System control block register map and reset values. The base address of the SCB register block is 0xE000 ED00 for register described in Table Table 53. SCB register map and reset values Offset Register CPUID... - Page 245 PM0214 Core peripherals Table 53. SCB register map and reset values (continued) Offset Register SHPR2 PRI11 0x1C Reserved Reset Value 0 0 0 0 0 0 0 0 SHPR3 PRI15 PRI14 0x20 Reserved Reset Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SHCSR 0x24 Reserved...
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Page 246: Systick Timer (Stk)
Core peripherals PM0214 SysTick timer (STK) The processor has a 24-bit system timer, SysTick, that counts down from the reload value to zero, reloads (wraps to) the value in the STK_LOAD register on the next clock edge, then counts down on subsequent clocks. When the processor is halted for debugging the counter does not decrement. -
Page 247: Systick Control And Status Register (Stk_Ctrl)
PM0214 Core peripherals 4.5.1 SysTick control and status register (STK_CTRL) Address offset: 0x00 Reset value: 0x0000 0000 Required privilege: Privileged The SysTick CTRL register enables the SysTick features. COUNT FLAG Reserved CLKSO TICK URCE ABLE Reserved Bits 31:17 Reserved, must be kept cleared. Bit 16 COUNTFLAG: Returns 1 if timer counted to 0 since last time this was read. -
Page 248: Systick Reload Value Register (Stk_Load)
Core peripherals PM0214 4.5.2 SysTick reload value register (STK_LOAD) Address offset: 0x04 Reset value: 0x0000 0000 Required privilege: Privileged RELOAD[23:16] Reserved RELOAD[15:0] Bits 31:24 Reserved, must be kept cleared. Bits 23:0 RELOAD: RELOAD value The LOAD register specifies the start value to load into the STK_VAL register when the counter is enabled and when it reaches 0. -
Page 249: Systick Current Value Register (Stk_Val)
PM0214 Core peripherals 4.5.3 SysTick current value register (STK_VAL) Address offset: 0x08 Reset value: 0x0000 0000 Required privilege: Privileged CURRENT[23:16] Reserved CURRENT[15:0] Bits 31:24 Reserved, must be kept cleared. Bits 23:0 CURRENT: Current counter value The VAL register contains the current value of the SysTick counter. Reads return the current value of the SysTick counter. -
Page 250: Systick Calibration Value Register (Stk_Calib)
Core peripherals PM0214 4.5.4 SysTick calibration value register (STK_CALIB) Address offset: 0x0C Reset value: 0x0000000 Required privilege: Privileged The CALIB register indicates the SysTick calibration properties. SKEW TENMS[23:16] Reserved TENMS[15:0] Bit 31 NOREF: NOREF flag. Reads as zero. Indicates that a separate reference clock is provided. The frequency of this clock is HCLK/8. -
Page 251: Systick Register Map
PM0214 Core peripherals 4.5.6 SysTick register map The table provided shows the SysTick register map and reset values. The base address of the SysTick register block is 0xE000 E010. Table 55. SysTick register map and reset values Offset Register STK_CTRL 0x00 Reserved Reserved... -
Page 252: Floating Point Unit (Fpu)
The following sections describe the floating-point system registers whose implementation is specific to this processor. Note: For more details on the IEEE standard and floating-point arithmetic (IEEE 754), refer to the AN4044 Application note. Available from website www.st.com. 252/262 PM0214 Rev 9... -
Page 253: Coprocessor Access Control Register (Cpacr)
PM0214 Core peripherals 4.6.1 Coprocessor access control register (CPACR) Address offset (from SCB): 0x88 Reset value: 0x0000000 Required privilege: Privileged The CPACR register specifies the access privileges for coprocessors. CP11 CP10 Reserved Reserved Reserved Bits 31:24 Reserved. Read as Zero, Write Ignore. Bits 23:20 CPn: [2n+1:2n] for n values 10 and 11. - Page 254 Core peripherals PM0214 Bit 31 ASPEN: Enables CONTROL<2> setting on execution of a floating-point instruction. This results in automatic hardware state preservation and restoration, for floating-point context, on exception entry and exit. 0: Disable CONTROL<2> setting on execution of a floating-point instruction. 1: Enable CONTROL<2>...
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Page 255: Floating-Point Context Address Register (Fpcar)
PM0214 Core peripherals 4.6.3 Floating-point context address register (FPCAR) Address offset: 0x08 Reset value: 0x0000000 Required privilege: Privileged The FPCAR register holds the location of the unpopulated floating-point register space allocated on an exception stack frame. ADDRESS[31:16] ADDRESS[15:3] Reserved Bits 31:3 ADDRESS: Location of unpopulated floating-point register space allocated on an exception stack frame. -
Page 256: Table 57. Effect Of A Floating-Point Comparison On The Condition Flags
Core peripherals PM0214 Bit 28 V: Overflow condition code flag. Floating-point comparison operations update this flag. For more details on the result, refer to Table 0: Operation did not result in an overflow 1: Operation resulted in an overflow. Bit 27 Reserved. Bit 26 AHP: Alternative half-precision control bit: 0: IEEE half-precision format selected. -
Page 257: Floating-Point Default Status Control Register (Fpdscr)
PM0214 Core peripherals 4.6.5 Floating-point default status control register (FPDSCR) Address offset: 0x0C Reset value: 0x0000000 Required privilege: Privileged The FPDSCR register holds the default values for the floating-point status control data. RMode Reserved Reserved Reserved Bits 31:27 Reserved, must be kept cleared. Bit 26 AHP: Default value for FPSCR.AHP Bit 25 DN: Default value for FPSCR.DN Bit 24 FZ: Default value for FPSCR.FZ... -
Page 258: Enabling And Clearing Fpu Exception Interrupts
Core peripherals PM0214 4.6.7 Enabling and clearing FPU exception interrupts The FPU exception flags are generating an interrupt through the interrupt controller. The FPU interrupt is globally controlled through the interrupt controller. A mask bit is also provided in the System Configuration Controller (SYSCFG), allowing to enable/disable individually each FPU flag interrupt generation. - Page 259 PM0214 Core peripherals sp = sp + 0x60; else if(lr == 0xFFFFFFED) sp = __get_PSP() + 0x60 ; fpscr_val = *(uint32_t*)sp; { check exception flags } fpscr_val &= (uint32_t)~0x8F ; // Clear all exception flags *(uint32_t*)sp = fpscr_val; __DMB() ; // FPU IRQ Handler void __asm FPU_IRQHandler(void) IMPORT...
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Page 260: Revision History
Revision history PM0214 Revision history Table 58. Document revision history Date Revision Changes 20-Feb-2012 Initial release. Changed reset value in Section 4.6.2: Floating-point context control register (FPCCR). 09-Jul-2012 Added Table 1: Applicable products. Added information on the STM32F3xxx Cortex-M4 processor. Added extra part numbers to Table 1: Applicable products. - Page 261 Revision Changes Updated the Introduction Reference documents to include the 24-Jun-2019 support for STM32H7 Series. Added STM32WL Series. Replaced SHCRS by SHCSR in Table 50: Summary of the system 18-Dec-2019 control block registers Table 53: SCB register map and reset values.
- Page 262 ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement.
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