ST STM32L4+ Series Reference Manual page 1049

RM0432
31.3.4 Charge transfer acquisition sequence
An example of a charge transfer acquisition sequence is detailed in
CLK_AHB
1
C
X
HiZ
0
1
C
S
HiZ
0
State
For higher flexibility, the charge transfer frequency is fully configurable. Both the pulse high
state (charge of C
be defined using the CTPH[3:0] and CTPL[3:0] bits in the TSC_CR register. The standard
range for the pulse high and low states duration is 500 ns to 2 µs. To ensure a correct
measurement of the electrode capacitance, the pulse high state duration must be set to
ensure that C
A dead time where both the sampling capacitor I/O and the channel I/O are in input floating
state is inserted between the pulse high and low states to ensure an optimum charge
transfer acquisition sequence. This state duration is 1 periods of HCLK.
At the end of the pulse high state and if the spread spectrum feature is enabled, a variable
number of periods of the SSCLK clock are added.
The reading of the sampling capacitor I/O, to determine if the voltage across C
reached the given threshold, is performed at the end of the pulse low state and its duration
is one period of HCLK.
Note: The following TSC control register configurations are forbidden:
•
bits PGPSC are set to '000' and bits CTPL are set to '0000'
•
bits PGPSC are set to '000' and bits CTPL are set to '0001'
•
bits PGPSC are set to '001' and bits CTPL are set to '0000'
Figure 244. Charge transfer acquisition sequence
Charge transfer frequency
Discharge Pulse high state
C and C (charge of C )
X S X
) and the pulse low state (transfer of charge from C
X
is always fully charged.
X
RM0432 Rev 6
Touch sensing controller (TSC)
Pulse low state
(charge transfer
from C to C )
X S
Figure 244.
MS30932V1
to C ) duration can
X S
has
S
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