ST STM32L4+ Series Reference Manual page 711

RM0432
21.6.15 ADC regular data register (ADC_DR)
Address offset: 0x40
Reset value: 0x0000 0000
31 30 29
Res. Res. Res. Res.
15 14 13
r r r
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:0 RDATA[15:0]: Regular data converted
These bits are read-only. They contain the conversion result from the last converted regular channel.
The data are left- or right-aligned as described in
21.6.16 ADC injected sequence register (ADC_JSQR)
Address offset: 0x4C
Reset value: 0x0000 0000
31 30 29
Res. JSQ4[4:0]
rw rw
15 14 13
JSQ2[1:0] Res.
rw rw
Bit 31 Reserved, must be kept at reset value.
Bits 30:26 JSQ4[4:0]: 4th conversion in the injected sequence
Note: The software is allowed to write these bits only when JADSTART=0 (which ensures that
Bit 25 Reserved, must be kept at reset value.
Bits 24:20 JSQ3[4:0]: 3rd conversion in the injected sequence
Note: The software is allowed to write these bits only when JADSTART=0 (which ensures that
Bit 19 Reserved, must be kept at reset value.
28 27 26 25
Res. Res. Res.
12 11 10 9
r r r r
28 27 26 25
Res.
rw rw rw
12 11 10 9
JSQ1[4:0]
rw rw rw rw
These bits are written by software with the channel number (0 to 18) assigned as the 4th in
the injected conversion sequence.
no injected conversion is ongoing).
These bits are written by software with the channel number (0 to 18) assigned as the 3rd in
the injected conversion sequence.
no injected conversion is ongoing).
24 23 22
Res. Res. Res.
8 7 6
RDATA[15:0]
r r r
Section 21.4.26: Data
24 23 22
JSQ3[4:0]
rw rw rw
8 7 6
JEXTEN[1:0]
rw rw rw
RM0432 Rev 6
Analog-to-digital converters (ADC)
21 20 19 18
Res. Res. Res. Res.
5 4 3 2
r r r r
management.
21 20 19 18
Res.
rw rw rw
5 4 3 2
JEXTSEL[3:0]
rw rw rw rw
17 16
Res. Res.
1 0
r r
17 16
JSQ2[4:2]
rw rw
1 0
JL[1:0]
rw rw
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