ST STM32L4+ Series Reference Manual page 700

Analog-to-digital converters (ADC)
Bit 12 OVRMOD: Overrun mode
This bit is set and cleared by software and configure the way data overrun is managed.
0: ADC_DR register is preserved with the old data when an overrun is detected.
1: ADC_DR register is overwritten with the last conversion result when an overrun is detected.
Note: The software is allowed to write this bit only when ADSTART=0 (which ensures that no regular
conversion is ongoing).
Bits 11:10 EXTEN[1:0]: External trigger enable and polarity selection for regular channels
These bits are set and cleared by software to select the external trigger polarity and enable the
trigger of a regular group.
00: Hardware trigger detection disabled (conversions can be launched by software)
01: Hardware trigger detection on the rising edge
10: Hardware trigger detection on the falling edge
11: Hardware trigger detection on both the rising and falling edges
Note: The software is allowed to write these bits only when ADSTART=0 (which ensures that no
regular conversion is ongoing).
Bits 9:6 EXTSEL[3:0]: External trigger selection for regular group
These bits select the external event used to trigger the start of conversion of a regular group:
0000: Event 0
0001: Event 1
0010: Event 2
0011: Event 3
0100: Event 4
0101: Event 5
0110: Event 6
0111: Event 7
...
1111: Event 15
Note: The software is allowed to write these bits only when ADSTART=0 (which ensures that no
regular conversion is ongoing).
Bit 5 ALIGN: Data alignment
This bit is set and cleared by software to select right or left alignment. Refer to
register, data alignment and offset (ADC_DR, OFFSETy, OFFSETy_CH, ALIGN)
0: Right alignment
1: Left alignment
Note: The software is allowed to write this bit only when ADSTART=0 and JADSTART=0 (which
ensures that no conversion is ongoing).
Bits 4:3 RES[1:0]: Data resolution
These bits are written by software to select the resolution of the conversion.
00: 12-bit
01: 10-bit
10: 8-bit
11: 6-bit
Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which
ensures that no conversion is ongoing).
700/2301 RM0432 Rev 6
RM0432
Section : Data