ST STM32L4+ Series Reference Manual page 893

RM0432
LTDC_SSCR
LTDC_BPCR
LTDC_AWCR
LTDC_TWCR
LTDC_GCR
LTDC_BCCR
LTDC_LIPCR
LTDC_CPSR
LTDC_CDSR
LTDC_LxWHPCR
LTDC_LxWVPCR
LTDC_LxCKCR
LTDC_LxPFCR
LTDC_LxCACR
LTDC_LxDCCR
LTDC_LxBFCR
LTDC_LxCLUTWR
Care must be taken while accessing the LTDC registers, the APB2 bus is stalled during:
• 6 PCKL2 periods + 5 LCD_CLK periods (five HCLK periods for register on AHB clock
domain) for register write access and update
•
7 PCKL2 periods + 5 LCD_CLK periods (five HCLK periods for register on AHB clock
domain) for register read access
For registers on PCLK2 clock domain, APB2 bus is stalled for six PCKL2 periods during the
register write accesses, and for seven PCKL2 periods during read accesses.
The LCD controller can be reset by setting the corresponding bit in the RCC_APB2RSTR
register. It resets the three clock domains.
29.5 LTDC programmable parameters
The LCD-TFT controller provides flexible configurable parameters. It can be enabled or
disabled through the LTDC_GCR register.
29.5.1 LTDC global configuration parameters
Synchronous timings
Figure 200
timings generator block presented in the block diagram
Table 194. Clock domain for each register (continued)
LTDC register
presents the configurable timing parameters generated by the synchronous
RM0432 Rev 6
LCD-TFT display controller (LTDC)
Clock domain
Pixel clock (LCD_CLK)
Figure 199. It generates the
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