ST STM32L4+ Series Reference Manual page 263

RM0432
Bits 13:11 PPRE2[2:0]: APB high-speed prescaler (APB2)
Bits 10:8 PPRE1[2:0]:APB low-speed prescaler (APB1)
Bits 7:4 HPRE[3:0]: AHB prescaler
Caution:
Bits 3:2 SWS[1:0]: System clock switch status
Bits 1:0 SW[1:0]: System clock switch
Set and cleared by software to control the division factor of the APB2 clock (PCLK2).
0xx: HCLK not divided
100: HCLK divided by 2
101: HCLK divided by 4
110: HCLK divided by 8
111: HCLK divided by 16
Set and cleared by software to control the division factor of the APB1 clock (PCLK1).
0xx: HCLK not divided
100: HCLK divided by 2
101: HCLK divided by 4
110: HCLK divided by 8
111: HCLK divided by 16
Set and cleared by software to control the division factor of the AHB clock.
Depending on the device voltage range, the software has to set
correctly these bits to ensure that the system frequency does not
exceed the maximum allowed frequency (for more details please refer to
Section 5.1.8: Dynamic voltage scaling
operation to these bits and before decreasing the voltage range, this
register must be read to be sure that the new value has been taken into
account.
0xxx: SYSCLK not divided
1000: SYSCLK divided by 2
1001: SYSCLK divided by 4
1010: SYSCLK divided by 8
1011: SYSCLK divided by 16
1100: SYSCLK divided by 64
1101: SYSCLK divided by 128
1110: SYSCLK divided by 256
1111: SYSCLK divided by 512
Set and cleared by hardware to indicate which clock source is used as system clock.
00: MSI oscillator used as system clock
01: HSI16 oscillator used as system clock
10: HSE used as system clock
11: PLL used as system clock
Set and cleared by software to select system clock source (SYSCLK).
Configured by HW to force MSI oscillator selection when exiting Standby or Shutdown mode.
Configured by HW to force MSI or HSI16 oscillator selection when exiting Stop mode or in
case of failure of the HSE oscillator, depending on STOPWUCK value.
00: MSI selected as system clock
01: HSI16 selected as system clock
10: HSE selected as system clock
11: PLL selected as system clock
RM0432 Rev 6
Reset and clock control (RCC)
management). After a write
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