ST STM32L4+ Series Reference Manual page 561

RM0432 Octo-SPI interface (OCTOSPI)
In order to assure enough "turn-around" time for changing the data signals from the output
mode to the input mode, there must be at least one dummy cycle when using the Dual-SPI,
the Quad-SPI or the Octal-SPI mode, to receive data from the external device.
It is recommended to have at least five dummy cycles when using memories with DQS
activated.
In Memory-mapped mode, the dummy cycles for the write operations are specified in the
OCTOSPI_WTCR register. The dummy cycles for the read operation are specified in the
regular register (OCTOSPI_TCR)
Data phase
During the data phase, any number of bytes can be sent to or received from the external
device.
In Indirect mode, the number of bytes to be sent/received is specified in the OCTOSPI_DLR
register. In this mode, the data to be sent to the external device must be written to the
OCTOSPI_DR register, while in Indirect-read mode the data received from the external
device is obtained by reading from the OCTOSPI_DR register.
In Automatic-polling mode, the number of bytes to be received is specified in the
OCTOSPI_DLR register and the data received from the external device can be obtained by
reading from the OCTOSPI_DR register.
In Memory-mapped mode, the data read or written, is sent or received directly over the AHB
to the Cortex core or to a DMA.
The data phase can send/receive 1 bit at a time (over SO/SI in Single-SPI mode), 2 bits at a
time (over IO0/IO1 in Dual-SPI mode), 4 bits at a time (over IO0 to IO3 in Quad-SPI mode)
or 8 bits at a time (over IO0 to IO7 in Octal SPI mode). This can be configured using the
DMODE[2:0] field of the OCTOSPI_CCR register.
The data can be sent or received in DTR mode (on each rising and falling edge of the clock)
setting the DDTR bit of OCTOSPI_CCR.
When DMODE[2:0] = 000, the data phase is skipped, and the command sequence finishes
immediately by raising the nCS. This configuration must be used only in Indirect-write mode.
In Memory-mapped mode, the data format for the write operation is specified in the
OCTOSPI_WCCR register. The data format for the read operation is specified in the regular
register OCTOSPI_CCR.
DQS usage
The DQS signal can be used for data strobing during the read transactions when the device
toggles the DQS aligned with the data.
The DQS management can be enabled by setting the DQS enable (DQSE) bit of
OCTOSPI_CCR.
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