ST STM32L4+ Series Reference Manual page 585

RM0432
19.6.2 OCTOSPI device configuration register 1 (OCTOSPI_DCR1)
Address offset: 0x0008
Reset value: 0x0000 0000
31 30 29 28
Res. Res. Res. Res.
15 14 13 12
Res. Res.
rw rw
Bits 31:27 Reserved, must be kept at reset value.
Bits 26:24 MTYP[2:0]: Memory type
This bit indicates the type of memory to be supported.
000: Micron mode, D0/D1 ordering in DTR 8-data-bit mode. Regular SPI protocol in
Octal/Quad/Dual/Single modes
Note: In this mode, DQS signal polarity is inverted with respect to the memory clock signal.
This is the default value and care must be taken to change MTYP[2:0] for memories different
from Micron.
001: Macronix mode, D1/D0 ordering in DTR 8-data-bit mode. Regular SPI protocol in
Octal/Quad/Dual/Single modes
010: Standard mode
011: Macronix RAM mode, D1/D0 ordering in DTR 8-data-bit mode. Regular SPI protocol in
Octal/Quad/Dual/Single modes with dedicated address mapping.
100: HyperBus memory mode, the protocol follows the HyperBus specification. 8-data-bit
DTR mode must be selected.
101: HyperBus register mode, addressing register space. The memory-mapped accesses in
this mode must be non-cacheable, or Indirect read/write modes must be used.
110-111: Reserved
Bits 23:21 Reserved, must be kept at reset value.
Bits 20:16 DEVSIZE[4:0]: Device size
This field defines the size of the external device using the following formula:
Number of bytes in device = 2
DEVSIZE+1 is effectively the number of address bits required to address the external device.
The device capacity can be up to 4 Gbytes (addressed using 32-bits) in Indirect mode, but
the addressable space in Memory-mapped mode is limited to 256 Mbytes.
In Regular-command mode, if DQM = 1, DEVSIZE[4:0] indicates the total capacity of the two
devices together.
Bits 15:14 Reserved, must be kept at reset value.
27 26 25 24
Res. MTYP[2:0]
rw rw rw
11 10 9 8
CSHT[5:0]
rw rw rw rw
RM0432 Rev 6
23 22 21
Res. Res. Res.
7 6 5
Res. Res. Res.
[DEVSIZE+1]
.
Octo-SPI interface (OCTOSPI)
20 19 18 17
DEVSIZE[4:0]
rw rw rw rw
4 3 2
DLYBY
Res. Res. FRCK
P
rw rw
16
rw
1 0
CKMO
DE
rw
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