ST STM32L4+ Series Reference Manual page 215

RM0432
5.3.10 Shutdown mode
The Shutdown mode allows to achieve the lowest power consumption. It is based on the
Deepsleep mode, with the voltage regulator disabled. The V
powered off. The PLL, the HSI16, the MSI, the LSI and the HSE oscillators are also
switched off.
SRAM1, SRAM2, SRAM3 and register contents are lost except for registers in the Backup
domain. The BOR is not available in Shutdown mode. No power voltage monitoring is
possible in this mode, therefore the switch to Backup domain is not supported.
I/O states in Shutdown mode
In the Shutdown mode, are by default in floating state. If the APC bit of PWR_CR3 register
has been set, the I/Os can be configured either with a pull-up (refer to PWR_PUCRx
registers (x=A,B,C,D,E,F,G,H), or with a pull-down (refer to PWR_PDCRx registers
(x=A,B,C,D,E,F,G,H)), or can be kept in analog state if none of the PWR_PUCRx or
PWR_PDCRx register has been set. The pull-down configuration has highest priority over
pull-up configuration in case both PWR_PUCRx and PWR_PDCRx are set for the same IO.
However this configuration is lost when exiting the Shutdown mode due to the power-on
reset.
Some I/Os (listed in
debug and can only be configured to their respective reset pull-up or pull-down state during
Standby mode setting their respective bit in the PWR_PUCRx or PWR_PDCRx registers to
'1', or will be configured to floating state if the bit is kept at '0'.
The RTC outputs on PC13 are functional in Shutdown mode. PC14 and PC15 used for LSE
are also functional. 5 wakeup pins (WKUPx, x=1,2...5) and the 3 RTC tampers are available.
Entering Shutdown mode
The Shutdown mode is entered according
SLEEPDEEP bit in the Cortex
Refer to
In Shutdown mode, the following features can be selected by programming individual
control bits:
•
real-time clock (RTC): this is configured by the RTCEN bit in the Backup domain
control register (RCC_BDCR). Caution: in case of VDD power-down the RTC content
will be lost.
•
external 32.768 kHz oscillator (LSE): this is configured by the LSEON bit in the Backup
domain control register (RCC_BDCR)
Exiting Shutdown mode
The Shutdown mode is exit according
occurs when exiting from Shutdown mode. All registers (except for the ones in the Backup
domain) are reset after wakeup from Shutdown.
Refer to
When exiting Shutdown mode, I/Os that were configured with pull-up or pull-down during
Shutdown through registers PWR_PUCRx or PWR_PDCRx will lose their configuration and
Section 8.3.1: General-purpose I/O
®
Table 35: Shutdown mode
Table 35: Shutdown mode
Entering low-power
-M4 System Control register is set.
for details on how to enter Shutdown mode.
Section : Exiting low-power
for more details on how to exit Shutdown mode.
RM0432 Rev 6
Power control (PWR)
domain is consequently
CORE
(GPIO)) are used for JTAG/SW
mode, when the
mode. A power-on reset
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