ST STM32L4+ Series Reference Manual page 270

Reset and clock control (RCC)
6.4.6 PLLSAI2 configuration register (RCC_PLLSAI2CFGR)
Address offset: 0x14
Reset value: 0x0000 1000
Access: no wait state, word, half-word and byte access
This register is used to configure the PLLSAI2 clock outputs according to the formulas:
• f(VCOSAI2 clock) = f(PLL clock input) × (PLLSAI2N / PLLSAI2M)
• f(PLLSAI2_P) = f(VCOSAI2 clock) / PLLSAI2PDIV
• f(PLLSAI2_R) = f(VCOSAI2 clock) / PLLSAI2R
31 30 29
PLLSAI2PDIV[4:0]
rw rw rw
15 14 13
Res.
rw rw
Bits 31:27 PLLSAI2PDIV[4:0]: PLLSAI2 division factor for PLLSAI2CLK
Bits 26:25 PLLSAI2R[1:0]: PLLSAI2 division factor for PLLLCDCLK (LTDC clock)
Bit 24 PLLSAI2REN: PLLSAI2 PLLLCDCLK output enable
Bit 23 Reserved, must be kept at reset value.
270/2301
28 27 26 25
PLLSAI2R[1:0]
rw rw rw rw
12 11 10 9
PLLSAI2N[6:0]
rw rw rw rw
Set and cleared by software to control the SAI1 or SAI2 clock frequency. PLLSAI2CLK
output clock
frequency = VCOSAI2 frequency / PLLSAI2PDIV.
00000: PLLSAI2CLK is controlled by the bit PLLSAI2P
00001: Reserved.
00010: PLLSAI2CLK = VCOSAI2 / 2
....
11111: PLLSAI2CLK = VCOSAI2 / 31
Set and cleared by software to control the frequency of the PLLSAI2 output clock
PLLLCDCLK. This output can be selected as ADC clock. These bits can be written only if
PLLSAI2 is disabled.
PLLLCDCLK output clock frequency = VCOSAI2 frequency / PLLSAI2R with PLLSAI2R = 2,
4, 6, or 8
00: PLLSAI2R = 2
01: PLLSAI2R = 4
10: PLLSAI2R = 6
11: PLLSAI2R = 8
Set and reset by software to enable the PLLLCDCLK output of the PLLSAI2 (used as clock
for ADC).
In order to save power, when the PLLLCDCLK output of the PLLSAI2 is not used, the value
of PLLSAI2REN should be 0.
0: PLLLCDCLK output disable
1: PLLLCDCLK output enable
24 23 22
PLLSAI
Res. PLLSAI2Q
2REN
rw
8 7 6
PLLSAI2M[3:0]
rw rw rw
RM0432 Rev 6
21 20 19 18
PLLSAI
Res. Res.
2QEN
5 4 3 2
Res. Res.
rw rw
RM0432
17 16
PLLSAI PLLSAI
2P 2PEN
rw rw
1 0
Res. Res.