ST STM32L4+ Series Reference Manual page 134

Embedded Flash memory (FLASH)
BANK Address
1FF01000
1FF01008
1FF01010
Bank 2
1FF01018
1FF01020
User and read protection option bytes
Flash memory address: 0x1FF0 0000
ST production value: 0xFFEF F8AA
31 30 29
Res. Res. Res. Res.
15 14 13
nRST_ nRST_ nRST_
Res.
SHDW STDBY STOP
r r
Bits 31:28 Reserved, must be kept at reset value.
134/2301
Table 14. Option byte organization (continued)
[63:56] [55:48]
Unused and
PCROP2_STRT[16]
Unused and
PCROP2_END[16]
WRP1A
Unused
_END
WRP2A
Unused
_END
28 27 26 25
n nSW SRAM2
BOOT0 BOOT0 _RST
r r r
12 11 10 9
Res. BOR_LEV[2:0]
r r r
Bit 27 nBOOT0: nBOOT0 option bit
0: nBOOT0 = 0
1: nBOOT0 = 1
Bit 26 nSWBOOT0: Software BOOT0
0: BOOT0 taken from the option bit nBOOT0
1: BOOT0 taken from PH3/BOOT0 pin
Bit 25 SRAM2_RST: SRAM2 Erase when system reset
0: SRAM2 erased when a system reset occurs
1: SRAM2 is not erased when a system reset occurs
Bit 24 SRAM2_PE: SRAM2 parity check enable
0: SRAM2 parity check enable
1: SRAM2 parity check disable
Bit 23 nBOOT1: Boot configuration
Together with the BOOT0 pin, this bit selects boot mode from the Flash main
memory, SRAM1 or the System memory. Refer to
configuration.
[47:40] [39:32]
Unused
PCROP2_STRT[15]
PCROP2_STRT[16]
PCROP2_END[15]
WRP1B
Unused
_STRT
WRP2B
Unused
_STRT
24 23 22
SRAM2 n
DBANK DB1M
_PE BOOT1
r r r
8 7 6
r r r
RM0432 Rev 6
[31:24] [23:16] [15:8]
Unused and
PCROP2_STRT[15]
Unused and
PCROP2_END[15]
PCROP2_END[16]
WRP1A
Unused Unused
_END
WRP2A
Unused Unused
_END
21 20 19
WWDG IWGD_
BFB2
_SW STDBY
r r r
5 4 3
RDP[7:0]
r r r
Section 2.6: Boot
RM0432
[7:0]
WRP1B
_STRT
WRP2B
_STRT
18 17 16
IWDG_ IWDG_
STOP SW
r r r
2 1 0
r r r