ST STM32L4+ Series Reference Manual page 658

Analog-to-digital converters (ADC)
Figure 123. AUTODLY=1, regular HW conversions interrupted by injected conversions
Regular
trigger
ADC state
RDY CH1
regular
EOC
EOS
ADC_DR
read access
ADC_DR
Injected
trigger
JEOS
ADC_JDR1
ADC_JDR2
by s/w
1. AUTDLY=1
2. Regular configuration: EXTEN[1:0]=01 (HW trigger), CONT=0, DISCEN=0, CHANNELS = 1, 2, 3
3. Injected configuration: JEXTEN[1:0]=01 (HW Trigger), JDISCEN=0, CHANNELS = 5,6
658/2301
(DISCEN=0; JDISCEN=0)
Ignored
DLY CH2 DLY
regular
DLY (CH1)
DLY (CH2)
D1
by h/w
RM0432 Rev 6
Not ignored
(occurs during injected sequence)
CH5 CH6 CH3
regular injected
injected
DLY (CH3)
D2
Ignored
DLY (inj)
Indicative timings
RM0432
DLY CH1 DLY
regular
DLY (CH1)
D3
D1
D5
D6
MS31021V2
CH2
regular