ST STM32L4+ Series Reference Manual page 432

Chrom-ART Accelerator controller (DMA2D)
13.5 DMA2D registers
13.5.1 DMA2D control register (DMA2D_CR)
Address offset: 0x0000
Reset value: 0x0000 0000
31 30 29
Res. Res. Res. Res.
15 14 13
Res. Res. CEIE CTCIE
rw
Bits 31:19 Reserved, must be kept at reset value.
Bits 18:16 MODE[2:0]: DMA2D mode
Bits 15:14 Reserved, must be kept at reset value.
Bit 13 CEIE: Configuration Error Interrupt Enable
Bit 12 CTCIE: CLUT transfer complete interrupt enable
Bit 11 CAEIE: CLUT access error interrupt enable
Bit 10 TWIE: Transfer watermark interrupt enable
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28 27 26 25
Res. Res. Res.
12 11 10 9
CAEIE TWIE TCIE
rw rw rw rw
These bits are set and cleared by software. They cannot be modified while a transfer is
ongoing.
000: Memory-to-memory (FG fetch only)
001: Memory-to-memory with PFC (FG fetch only with FG PFC active)
010: Memory-to-memory with blending (FG and BG fetch with PFC and blending)
011: Register-to-memory (no FG nor BG, only output stage active)
100: Memory-to-memory with Blending and fixed color FG (BG fetch only with FG and
BG PFC active)
101: Memory-to-memory with Blending and fixed color BG (BG fetch only with FG and
BG PFC active)
others: meaningless
This bit is set and cleared by software.
0: CE interrupt disable
1: CE interrupt enable
This bit is set and cleared by software.
0: CTC interrupt disable
1: CTC interrupt enable
This bit is set and cleared by software.
0: CAE interrupt disable
1: CAE interrupt enable
This bit is set and cleared by software.
0: TW interrupt disable
1: TW interrupt enable
24 23 22
Res. Res. Res.
8 7 6
TEIE Res. LOM
rw rw
RM0432 Rev 6
21 20 19 18
Res. Res. Res.
rw
5 4 3 2
Res. Res. Res. ABORT SUSP
rs
RM0432
17 16
MODE[2:0]
rw rw
1 0
START
rw rs