ST STM32L4+ Series Reference Manual page 906

LCD-TFT display controller (LTDC)
Bit 31 HSPOL: horizontal synchronization polarity
This bit is set and cleared by software.
0: horizontal synchronization polarity is active low.
1: horizontal synchronization polarity is active high.
Bit 30 VSPOL: vertical synchronization polarity
This bit is set and cleared by software.
0: vertical synchronization is active low.
1: vertical synchronization is active high.
Bit 29 DEPOL: not data enable polarity
This bit is set and cleared by software.
0: not data enable polarity is active low.
1: not data enable polarity is active high.
Bit 28 PCPOL: pixel clock polarity
This bit is set and cleared by software.
0: pixel clock polarity is active low.
1: pixel clock is active high.
Bits 27:17 Reserved, must be kept at reset value.
Bit 16 DEN: dither enable
This bit is set and cleared by software.
0: dither disable
1: dither enable
Bit 15 Reserved, must be kept at reset value.
Bits 14:12 DRW[2:0]: dither red width
These bits return the Dither Red Bits.
Bit 11 Reserved, must be kept at reset value.
Bits 10:8 DGW[2:0]: dither green width
These bits return the dither green bits.
Bit 7 Reserved, must be kept at reset value.
Bits 6:4 DBW[2:0]: dither blue width
These bits return the dither blue bits.
Bits 3:1 Reserved, must be kept at reset value.
Bit 0 LTDCEN: LCD-TFT controller enable
This bit is set and cleared by software.
0: LTDC disable
1: LTDC enable
906/2301 RM0432 Rev 6
RM0432