ST STM32L4+ Series Reference Manual page 882

Digital filter for sigma delta modulators (DFSDM)
Table 191. DFSDM register map and reset values (continued)
Register
Offset
name
DFSDM_
CH3CFGR1
0x60
reset value
DFSDM_
CH3CFGR2
0x64
reset value 0
DFSDM_
CH3AWSCDR
0x68
reset value
DFSDM_
CH3WDATR
0x6C
reset value
DFSDM_
CH3DATINR
0x70
reset value 0
DFSDM_
CH3DLYR
0x74
reset value
0x78 -
Reserved
0x7C
DFSDM_
CH4CFGR1
0x80
reset value
DFSDM_
CH4CFGR2
0x84
reset value 0
DFSDM_
CH4AWSCDR
0x88
reset value
DFSDM_
CH4WDATR
0x8C
reset value
DFSDM_
CH4DATINR
0x90
reset value 0
DFSDM_
CH4DLYR
0x94
reset value
0x98 -
Reserved
0x9C
882/2301
0 0 0 0 0 0 0 0 0
0 0
INDAT1[15:0]
0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0
0 0
INDAT1[15:0]
0 0 0 0 0 0 0 0 0
0 0
OFFSET[23:0]
0 0 0 0 0 0 0 0
AWFOSR[4:0] BKSCD[3:0]
0 0 0 0 0 0 0
0 0
0 0 0 0 0 0 0 0
0 0
OFFSET[23:0]
0 0 0 0 0 0 0 0
AWFOSR[4:0] BKSCD[3:0]
0 0 0 0 0 0 0
0 0
0 0 0 0 0 0 0 0
RM0432 Rev 6
0 0 0 0 0 0
DTRBS[4:0]
0 0 0 0 0 0 0 0 0
0 0 0 0 0
WDATA[15:0]
0 0 0 0 0 0 0 0 0
INDAT0[15:0]
0 0 0 0 0 0 0 0 0
0
0 0 0 0 0 0
DTRBS[4:0]
0 0 0 0 0 0 0 0 0
0 0 0 0 0
WDATA[15:0]
0 0 0 0 0 0 0 0 0
INDAT0[15:0]
0 0 0 0 0 0 0 0 0
0
RM0432
0 0 0 0
0 0
SCDT[7:0]
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
PLSSKP[5:0]
0 0 0 0 0
0 0 0 0
0 0
SCDT[7:0]
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
PLSSKP[5:0]
0 0 0 0 0