ST STM32L4+ Series Reference Manual page 157

RM0432
3.7.7 Flash ECC register (FLASH_ECCR)
Address offset: 0x18
Reset value: 0x0000 0000
Access: no wait state when no Flash memory operation is on going, word, half-word and
byte access
31 30 29 28
ECCD
ECCD ECCC ECCD2
2
rc_w1 rc_w1 rc_w1 rc_w1
r r r
Bits 27:25 Reserved, must be kept at reset value.
27 26 25
Res. Res. Res.
r r r
Bit 31 ECCD: ECC detection
DBANK=0
Set by hardware when two ECC errors have been detected (only if
ECCC/ECCC2/ECCD/ ECCD2 are previously cleared). When this bit is set, a
NMI is generated.
Cleared by writing 1.
DBANK=1
Set by hardware when two ECC errors have been detected on 64-bits LSB (bits
63:0) (only if ECCC/ECCC2/ECCD/ ECCD2 are previously cleared). When this
bit is set, a NMI is generated.
Cleared by writing 1.
Bit 30 ECCC: ECC correction
Set by hardware when one ECC error has been detected and corrected (only if
ECCC/ECCC2/ECCD/ECCD2 are previously cleared). An interrupt is generated
if ECCIE is set.
Cleared by writing 1.
Bit 29 ECCD2: ECC2 detection
DBANK=0
Set by hardware when two ECC errors have been detected on 64-bits MSB
(bits127:64). This bit is set (only if ECCC/ECCC2/ECCD/ECCD2 are previously
cleared). When this bit is set, a NMI is generated.
Cleared by writing 1.
DBANK=1
Reserved, must be kept at reset value.
Bit 28 ECCC2: ECC correction
DBANK=0
Set by hardware when one ECC error has been detected and corrected on 64-
bits MSB (bits127:64). This bit is set (only if ECCC/ECCC2/ECCD/ECCD2 are
previously cleared). An interrupt is generated if ECCIE is set.
Cleared by writing 1.
DBANK=1
Reserved, must be kept at reset value.
24 23 22
ECCC SYSF_
Res.
IE ECC
rw r
ADDR_ECC[15:0]
r r r r
RM0432 Rev 6
Embedded Flash memory (FLASH)
21 20 19 18
BK
ADDR_ECC[20:16]
_ECC
r r r r
r r r r
17 16
r r
r r
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