ST STM32L4+ Series Reference Manual page 666

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Analog-to-digital converters (ADC)

Table 137. Maximum output results versus N and M (gray cells indicate truncation)

There are no changes for conversion timings in oversampled mode: the sample time is

maintained equal during the whole oversampling sequence. A new data is provided every N

conversions, with an equivalent delay equal to N x T

set as follow:

The end of the sampling phase (EOSMP) is set after each sampling phase

The end of conversion (EOC) occurs once every N conversions, when the

oversampled result is available

The end of sequence (EOS) occurs once the sequence of oversampled data is

completed (i.e. after N x sequence length conversions total)

ADC operating modes supported when oversampling (single ADC mode)

In oversampling mode, most of the ADC operating modes are maintained:

Single or continuous mode conversions

ADC conversions start either by software or with triggers

ADC stop during a conversion (abort)

Data read via CPU or DMA with overrun detection

Low-power modes (AUTDLY)

Programmable resolution: in this case, the reduced conversion values (as per RES[1:0]

bits in ADC_CFGR1 register) are accumulated, truncated, rounded and shifted in the

same way as 12-bit conversions are

The alignment mode is not available when working with oversampled data. The ALIGN bit in

ADC_CFGR1 is ignored and the data are always provided right-aligned.

Offset correction is not supported in oversampling mode. When ROVSE and/or JOVSE bit is

set, the value of the OFFSETy_EN bit in ADC_OFRy register is ignored (considered as

0x3FFC 0x1FFE

0x3FFC 0x1FFE

0x3FFC 0x1FFE

0xFFC0 0xFFE0

0xFFC0 0xFFE0

0x3FFC 0x1FFE

0x3FFC 0x1FFE

RM0432 Rev 6

0x3FFC 0x1FFE

0x3FFC 0x1FFE

). The flags are

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