ST STM32L4+ Series Reference Manual page 287

RM0432
Bit 2 DMAMUX1EN: DMAMUX1 clock enable
Bit 1 DMA2EN: DMA2 clock enable
Bit 0 DMA1EN: DMA1 clock enable
6.4.17 AHB2 peripheral clock enable register (RCC_AHB2ENR)
Address offset: 0x4C
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access
Note: When the peripheral clock is not active, the peripheral registers read or write access is not
supported.
31 30 29
Res. Res. Res. Res.
15 14 13
DCMIE OTGFS
PKAEN ADCEN
N
rw rw rw
Bits 31:24 Reserved, must be kept at reset value.
Bit 23 SDMMC2EN: SDMMC2 clock enable
Set and cleared by software.
0: SDMMC2 clock disabled
1: SDMMC2 clock enabled
Bit 22 SDMMC1EN: SDMMC1 clock enable
Set and cleared by software.
0: SDMMC1 clock disabled
1: SDMMC1 clock enabled
Bit 21 Reserved, must be kept at reset value.
Bit 20 OSPIMEN: OctoSPI IO manager clock enable
Set and cleared by software.
0: OctoSPI IO manager clock disabled
1: OctoSPI IO manager clock enabled
Bit 19 Reserved, must be kept at reset value.
Set and reset by software.
0: DMAMUX1 clock disabled
1: DMAMUX1 clock enabled
Set and cleared by software.
0: DMA2 clock disable
1: DMA2 clock enable
Set and cleared by software.
0: DMA1 clock disable
1: DMA1 clock enable
28 27 26 25
Res. Res. Res.
12 11 10 9
Res. Res. Res.
EN
rw
24 23 22
SDMM SDMM
Res.
C2EN C1EN
rw rw
8 7 6
GPIOIE GPIOH GPIOG GPIOF
N EN EN
rw rw rw
RM0432 Rev 6
Reset and clock control (RCC)
21 20 19 18
RNG
OSPIM
Res. Res.
EN
EN
rw rw
5 4 3 2
GPIOE GPIOD GPIOC
EN EN EN EN
rw rw rw rw
17 16
HASHE
AESEN
N
rw rw
1 0
GPIOB GPIOA
EN EN
rw rw
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