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Parallel synchronous slave interface (PSSI) applied to STM32L4P5xx and STM32LQ5xx only
25.5.6
PSSI interrupt clear register (PSSI_ICR)
Address offset: 0x14
Reset value: 0x0000 0000
31
30
29
Res.
Res.
Res.
Res.
15
14
13
Res.
Res.
Res.
Res.
The PSSI_ICR register is write-only. Writing a 1 into a bit of this register clears the
corresponding bit in the PSSI_RIS and PSSI_MIS registers. Writing a 0 has no effect.
Reading this register always gives zeros.
Bits 31:2 Reserved, must be kept at reset value.
802/2301
Bits 31:2 Reserved, must be kept at reset value.
Bit 1 OVR_MIS: Data buffer overrun/underrun masked interrupt status
This bit is set to 1 only when PSSI_IER/OVR_IE and PSSI_RIS/OVR_RIS are
both set to 1.
0: No interrupt is generated when an overrun/underrun error occurs
1: An interrupt is generated if there is either an overrun or an underrun error
and the OVR_IE bit is set in PSSI_IER.
Bit 0 Reserved, must be kept at reset value.
28
27
26
25
Res.
Res.
Res.
12
11
10
9
Res.
Res.
Res.
Bit 1 OVR_ISC: Data buffer overrun/underrun interrupt status clear
Writing this bit to 1 clears the OVR_RIS bit in PSSI_RIS.
Bit 0 Reserved, must be kept at reset value.
24
23
22
Res.
Res.
Res.
8
7
6
Res.
Res.
Res.
RM0432 Rev 6
21
20
19
18
Res.
Res.
Res.
Res.
5
4
3
2
Res.
Res.
Res.
Res.
17
16
Res.
Res.
1
0
Res.
w
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