ST STM32L4+ Series Reference Manual page 592

Octo-SPI interface (OCTOSPI)
19.6.12 OCTOSPI polling status match register (OCTOSPI_PSMAR)
Address offset: 0x0088
Reset value: 0x0000 0000
31 30 29 28
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15 14 13 12
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Bits 31:0 MATCH[31: 0]: Status match
Value to be compared with the masked status register to get a match
This field can be written only when BUSY = 0.
19.6.13 OCTOSPI polling interval register (OCTOSPI_PIR)
Address offset: 0x0090
Reset value: 0x0000 0000
31 30 29 28
Res. Res. Res. Res.
15 14 13 12
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Bits 31:16 Reserved, must be kept at reset value.
Bits 15:0 INTERVAL[15: 0]: Polling interval
Number of CLK cycle between a read during the automatic polling phases
This field can be written only when BUSY = 0.
19.6.14 OCTOSPI communication configuration register (OCTOSPI_CCR)
Address offset: 0x0100
Reset value: 0x0000 0000
31 30 29 28
SIOO Res. DQSE Res.
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15 14 13 12
Res. Res. ADSIZE[1:0]
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592/2301
27 26 25 24
MATCH[31:16]
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11 10 9 8
MATCH[15:0]
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27 26 25 24
Res. Res. Res. Res.
11 10 9 8
INTERVAL[15:0]
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27 26 25 24
DDTR DMODE[2:0]
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11 10 9 8
ADDT
ADMODE[2:0]
R
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RM0432 Rev 6
23 22 21 20
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7 6 5 4
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23 22 21 20
Res. Res. Res. Res.
7 6 5 4
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23 22 21 20
Res. Res. ABSIZE[1:0]
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7 6 5 4
Res. Res. ISIZE[1:0]
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RM0432
19 18 17
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3 2 1
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19 18 17
Res. Res. Res. Res.
3 2 1
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19 18 17
ABDTR ABMODE[2:0]
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3 2 1
IDTR IMODE[2:0]
rw rw rw
16
rw
0
rw
16
0
rw
16
rw
0
rw