ST STM32L4+ Series Reference Manual page 660

Analog-to-digital converters (ADC)
Figure 125. AUTODLY=1, regular continuous conversions interrupted by injected conversions
(1)
ADSTART
ADC
RDY CH1
state
regular
EOC
EOS
ADC_DR read access
ADC_DR
Injected
trigger
JEOS
ADC_JDR1
ADC_JDR2
by s/w
1. AUTDLY=1
2. Regular configuration: EXTEN[1:0]=00 (SW trigger), CONT=1, DISCEN=0, CHANNELS = 1, 2, 3
3. Injected configuration: JEXTEN[1:0]=01 (HW Trigger), JDISCEN=0, CHANNELS = 5,6
Figure 126. AUTODLY=1 in auto- injected mode (JAUTO=1)
(1)
ADSTART
ADC state RDY CH1
regular
EOC
EOS
ADC_DR read access
ADC_DR
JEOS
ADC_JDR1
ADC_JDR2
by s/w
1. AUTDLY=1
2. Regular configuration: EXTEN[1:0]=00 (SW trigger), CONT=1, DISCEN=0, CHANNELS = 1, 2
3. Injected configuration: JAUTO=1, CHANNELS = 5,6
660/2301
CH2 DLY
DLY
regular
DLY (CH1) DLY (CH2)
D1
by h/w
No delay
DLY (CH1) CH2
regular
D1
by h/w
RM0432 Rev 6
CH5 CH6 DLY
injected injected
D2
Ignored
DLY (inj)
Indicative timings
CH5 CH6 DLY (inj)
injected injected
D2
DLY CH1
CH3
regular
regular
DLY (CH3)
D3
D5
D6
DLY(CH2) CH3 DLY
regular
D5
D6
Indicative timings
RM0432
MS31023V3
CH1
regular
D3
MS31024V3