ST STM32L4+ Series Reference Manual page 807

RM0432
¾ V
REFINT
V
REFINT
DAC Channel1
DAC Channel2
PB1
PC4
PB4
PB6
¼ V
REFINT
½ V
REFINT
¾ V
REFINT
V
REFINT
DAC Channel1
DAC Channel2
PB3
PB7
26.3.3 COMP reset and clocks
The COMP clock provided by the clock controller is synchronous with the APB2 clock.
There is no clock enable control bit provided in the RCC controller. Reset and clock enable
bits are common for COMP and SYSCFG.
Important: The polarity selection logic and the output redirection to the port works
independently from the APB2 clock. This allows the comparator to work even in Stop mode.
26.3.4 Comparator LOCK mechanism
The comparators can be used for safety purposes, such as over-current or thermal
protection. For applications having specific functional safety requirements, it is necessary to
insure that the comparator programming cannot be altered in case of spurious register
access or program counter corruption.
Table 172. COMP1 input minus assignment (continued)
COMP1_INM
Table 173. COMP2 input plus assignment
COMP2_INP
Table 174. COMP2 input minus assignment
COMP2_INM
RM0432 Rev 6
Comparator (COMP)
COMP1_INMSEL[2:0]
010
011
100
101
110
111
COMP2_INPSEL
0
1
COMP2_INMSEL[2:0]
000
001
010
011
100
101
110
111
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