ST STM32L4+ Series Reference Manual page 527

RM0432
In Burst mode, there are two timing configurations for the NOR Flash NWAIT signal:
•
The Flash memory asserts the NWAIT signal one data cycle before the wait state
(default after reset).
•
The Flash memory asserts the NWAIT signal during the wait state
The FMC supports both NOR Flash wait state configurations, for each chip select, thanks to
the WAITCFG bit in the FMC_BCRx registers (x = 0..3).
A[25:16]
NWAIT
(WAITCFG = 0)
NWAIT
(WAITCFG = 1)
A/D[15:0]
Figure 63. Wait configuration waveforms
HCLK
CLK
addr[25:16]
NADV
addr[15:0]
Flexible static memory controller (FSMC)
Memory transaction = burst of 4 half words
data data
RM0432 Rev 6
inserted wait state
data
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