ST STM32L4+ Series Reference Manual page 647

RM0432
RES
(bits)
12
10
8
6
21.4.23 End of conversion, end of sampling phase (EOC, JEOC, EOSMP)
The ADC notifies the application for each end of regular conversion (EOC) event and each
injected conversion (JEOC) event.
The ADC sets the EOC flag as soon as a new regular conversion data is available in the
ADC_DR register. An interrupt can be generated if bit EOCIE is set. EOC flag is cleared by
the software either by writing 1 to it or by reading ADC_DR.
The ADC sets the JEOC flag as soon as a new injected conversion data is available in one
of the ADC_JDRy register. An interrupt can be generated if bit JEOCIE is set. JEOC flag is
cleared by the software either by writing 1 to it or by reading the corresponding ADC_JDRy
register.
The ADC also notifies the end of Sampling phase by setting the status bit EOSMP (for
regular conversions only). EOSMP flag is cleared by software by writing 1 to it. An interrupt
can be generated if bit EOSMPIE is set.
21.4.24 End of conversion sequence (EOS, JEOS)
The ADC notifies the application for each end of regular sequence (EOS) and for each end
of injected sequence (JEOS) event.
The ADC sets the EOS flag as soon as the last data of the regular conversion sequence is
available in the ADC_DR register. An interrupt can be generated if bit EOSIE is set. EOS
flag is cleared by the software either by writing 1 to it.
The ADC sets the JEOS flag as soon as the last data of the injected conversion sequence is
complete. An interrupt can be generated if bit JEOSIE is set. JEOS flag is cleared by the
software either by writing 1 to it.
Table 132. T
T
SAR
(ADC clock cycles)
12.5 ADC clock cycles
10.5 ADC clock cycles
8.5 ADC clock cycles
6.5 ADC clock cycles
timings depending on resolution
SAR
T
CONV
T (ns) at
SAR
(with Sampling Time=
F = 30 MHz
ADC
2.5 ADC clock cycles)
416.67 ns 15 ADC clock cycles
350.0 ns 13 ADC clock cycles
203.33 ns 11 ADC clock cycles
216.67 ns 9 ADC clock cycles
RM0432 Rev 6
Analog-to-digital converters (ADC)
(ADC clock cycles)
T (ns) at
CONV
F = 30 MHz
ADC
500.0 ns
433.33 ns
366.67 ns
300.0 ns
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