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DSI Host (DSIHOST) applied to STM32L4R9xx and STM32L4S9xx only
30.16.10 DSI Wrapper PHY Configuration Register 4 (DSI_WPCR4)
Address offset: 0x0428
Reset value: 0x0000 0000
Note:
This register shall be programmed only when DSI is stopped (CR. DSIEN=0 and
DSI_CR.EN = 0).
31
30
29
Res.
Res.
Res.
Res.
15
14
13
Res.
Res.
Res.
Res.
Bits 31: 8 Reserved
Bits 7:0 TCLKPOST: t
30.16.11 DSI Wrapper Regulator and PLL Control Register (DSI_WRPCR)
Address offset: 0x0430
Reset value: 0x0000 0000
31
30
29
Res.
Res.
Res.
Res.
15
14
13
Res.
IDF[3:0]
rw
Bits 31: 25 Reserved
Bit 24 REGEN: Regulator Enable
Bits 23: 18 Reserved
Bits 17:16 ODF: PLL Output Division Factor
1038/2301
28
27
26
25
Res.
Res.
Res.
12
11
10
9
Res.
Res.
Res.
CLK-POST
This field defines the t
is used by the D-PHY when the TCLKPOSTEN bit of the DSI_WPCR0 is set.
TCLKPOST = 2 x t
CLK-POST
TCLKPOSTEN bit of the DSI_WPCR0 is reset is 200, i.e. 100 ns + 120*UI.
28
27
26
25
Res.
Res.
Res.
12
11
10
9
Res.
Res.
This bit enables the DPHY regulator:
0: regulator disabled
1: regulator enabled
This field configures the PLL Output Division Factor:
00: PLL output divided by 1.
01: PLL output divided by 2.
10: PLL output divided by 4.
11: PLL output divided by 8.
24
23
22
Res.
Res.
Res.
8
7
6
Res.
has specified in the MIPI
CLK-POST
expressed in ns.The default value used by the D-PHY when
24
23
22
REGEN
Res.
Res.
rw
8
7
6
RM0432 Rev 6
21
20
19
Res.
Res.
Res.
5
4
3
TCLKPOST[7:0]
rw
®
D-PHY specification. This value
21
20
19
Res.
Res.
Res.
5
4
3
NDIV[6:0]
rw
RM0432
18
17
16
Res.
Res.
Res.
2
1
0
18
17
16
Res.
ODF[1:0]
rw
2
1
0
Res.
PLLEN
rw
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