ST STM32L4+ Series Reference Manual page 1034

DSI Host (DSIHOST) applied to STM32L4R9xx and STM32L4S9xx only
Bit 11 HSIDL1: Invert the High-Speed data signal on Data Lane 1
Bit 10 HSIDL0: Invert the High-Speed data signal on Data Lane 0
Bit 9 HSICL: Invert High-Speed data signal on Clock Lane
Bit 8 SWDL1: Swap Data Lane 1 pins
Bit 7 SWDL0: Swap Data Lane 0 pins
Bit 6 SWCL: Swap Clock Lane pins
Bits 5:0 UIX4: Unit Interval multiplied by 4
30.16.7 DSI Wrapper PHY Configuration Register 1 (DSI_WPCR1)
Address offset: 0x041C
Reset value: 0x0000 0000
Note: This register shall be programmed only when DSI is stopped (CR. DSIEN=0 and
CR.EN = 0).
31 30 29 28
Res. Res. Res. Res.
15 14 13 12
Res. Res. Res. SDDC
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This bit invert the High-Speed data signal on data lane 1:
0: Normal data signal configuration.
1: Inverted data signal configuration.
This bit invert the High-Speed data signal on clock lane:
0: Normal data signal configuration.
1: Inverted data signal configuration.
This bit invert the High-Speed data signal on clock lane:
0: Normal data configuration.
1: Inverted data configuration.
This bit swap the pins on clock lane
0: Regular clock lane pin configuration.
1: Swapped clock lane pin.
This bit swap the pins on data lane 0:
0: Regular clock lane pin configuration.
1: Swapped clock lane pin.
This bit swap the pins on clock lane:
0: Regular clock lane pin configuration.
1: Swapped clock lane pin.
This field defines the bit period in High-Speed mode in unit of 0.25 ns.
As an example, if the unit interval is 3ns, a value of twelve (0x0C) should be driven to this
input. This value is used to generate delays. If the period is not a multiple of 0.25ns, the
value driven should be rounded down. For example, a 600Mbit/s link uses a unit interval
of 1.667 ns. Multiplying by four results in 6.667. In this case, a value of 6 (not 7) should be
driven onto the ui_x4 input.
27 26 25 24
Res. LPRXFT[1:0] Res.
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11 10 9
Res. Res. LPSRDL[1:0]
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23 22 21
Res. FLPRXLPM Res.
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8 7 6
LPSRCL[1:0] Res.
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RM0432 Rev 6
20 19 18
Res. HSTXSRCDL[1:0] HSTXSRCCL[1:0]
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5 4 3 2
Res. HSTXDDL[1:0]
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RM0432
17 16
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1 0
HSTXDCL[1:0]
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