ST STM32L4+ Series Reference Manual page 705

RM0432
Bits 31:27 Reserved, must be kept at reset value.
Bits 26:0 SMP[18:10][2:0]: Channel x sampling time selection
These bits are written by software to select the sampling time individually for each channel.
During sampling cycles, the channel selection bits must remain unchanged.
000: 2.5 ADC clock cycles
001: 6.5 ADC clock cycles
010: 12.5 ADC clock cycles
011: 24.5 ADC clock cycles
100: 47.5 ADC clock cycles
101: 92.5 ADC clock cycles
110: 247.5 ADC clock cycles
111: 640.5 ADC clock cycles
Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0
21.6.8 ADC watchdog threshold register 1 (ADC_TR1)
Address offset: 0x20
Reset value: 0x0FFF 0000
31 30 29
Res. Res. Res. Res.
15 14 13
Res. Res. Res. Res.
Bits 31:28 Reserved, must be kept at reset value.
Bits 27:16 HT1[11:0]: Analog watchdog 1 higher threshold
These bits are written by software to define the higher threshold for the analog watchdog 1.
Refer to
AWD2CH, AWD3CH, AWD_HTx, AWD_LTx, AWDx)
Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which
ensures that no conversion is ongoing).
Bits 15:12 Reserved, must be kept at reset value.
Bits 11:0 LT1[11:0]: Analog watchdog 1 lower threshold
These bits are written by software to define the lower threshold for the analog watchdog 1.
Refer to
AWD2CH, AWD3CH, AWD_HTx, AWD_LTx, AWDx)
Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which
ensures that no conversion is ongoing).
(which ensures that no conversion is ongoing).
Some channels are not connected physically. Keep the corresponding SMPx[2:0]
setting to the reset value.
28 27 26 25
rw rw rw
12 11 10 9
rw rw rw
Section 21.4.29: Analog window watchdog (AWD1EN, JAWD1EN, AWD1SGL, AWD1CH,
Section 21.4.29: Analog window watchdog (AWD1EN, JAWD1EN, AWD1SGL, AWD1CH,
24 23 22
HT1[11:0]
rw rw rw
8 7 6
LT1[11:0]
rw rw rw
RM0432 Rev 6
Analog-to-digital converters (ADC)
21 20 19 18
rw rw rw rw
5 4 3 2
rw rw rw rw
17 16
rw rw
1 0
rw rw
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