ST STM32L4+ Series Reference Manual page 556

Octo-SPI interface (OCTOSPI)
19.3 OCTOSPI implementation
The table below describes the OCTOSPI implementation on STM32L4+ Series devices. The
full list of features is implemented in STM32L4P5xx and STM32L4Q5xx devices, while
STM32L4Rxxx and STM32L4Sxxx devices support a reduced set of features
.
Hyperbus standard compliant
Xcella standard compliant
XSPI (JEDEC251ES) standard compliant
®
AMBA AHB compliant interface
Supported functional modes: Indirect, Status polling,
and Memory-mapped
Read and write support in Memory-mapped mode
Dual-quad mode support
SDR (single-data rate) and DTR (double-transfer
rate) support
Data strobe (DS,DQS) support
Fully programmable opcode
Fully programmable frame format
Integrated FIFO for reception and transmission
8, 16, and 32-bit data accesses
Interrupt on FIFO threshold, timeout, operation
complete, and access error
Compliant with dual-OCTOSPI arbiter
(communication regulation feature)
Extended CSHT high time minimum duration
Refresh counter
HyperBus differential clock mode
Micron memory type (MTYP = 000) support
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Table 119. OCTOSPI implementation on STM32L4+ Series
OCTOSPI feature
RM0432 Rev 6
STM32L4P5xx and
STM32L4Q5xx
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
RM0432
STM32L4Rxxx and
STM32L4Sxxx
X
X
X
X
X
X
X
X
X
X
X
X
X
X
-
-
-
-
-