ST STM32L4+ Series Reference Manual page 284

Reset and clock control (RCC)
Bits 4:2 Reserved, must be kept at reset value.
Bit 1 I2C4RST: I2C4 reset
Set and cleared by software
0: No effect
1: Reset I2C4
Bit 0 LPUART1RST: Low-power UART 1 reset
6.4.15 APB2 peripheral reset register (RCC_APB2RSTR)
Address offset: 0x40
Reset value: 0x00000 0000
Access: no wait state, word, half-word and byte access
31 30 29
Res. Res. Res. Res.
15 14 13
USART TIM8R SPI1R
Res.
1RST ST
rw rw
Bits 31:28 Reserved, must be kept at reset value.
Bit 27 DSIRST: DSI reset
Bit 26 LTDCRST: LCD-TFT reset
Bit 25 Reserved, must be kept at reset value.
Bit 24 DFSDM1RST: Digital filters for sigma-delta modulators (DFSDM1) reset
Bit 23 Reserved, must be kept at reset value.
Bit 22 SAI2RST: Serial audio interface 2 (SAI2) reset
284/2301
Set and cleared by software.
0: No effect
1: Reset LPUART1
28 27 26 25
DSIRS LTDCR
Res.
T ST
rw rw
12 11 10 9
TIM1R
Res. Res.
ST ST
rw rw
Set and cleared by software.
0: No effect
1: Reset DSI
Set and cleared by software.
0: No effect
1: Reset LCD-TFT
Set and cleared by software.
0: No effect
1: Reset DFSDM1
Set and cleared by software.
0: No effect
1: Reset SAI2
24 23 22
DFSD SAI2R SAI1R
Res.
M1RST ST
rw rw
8 7 6
Res. Res. Res.
RM0432 Rev 6
21 20 19 18
TIM17
Res. Res.
ST RST
rw rw
5 4 3 2
Res. Res. Res. Res.
RM0432
17 16
TIM16 TIM15
RST RST
rw rw
1 0
SYSCF
Res.
GRST
rw