ST STM32L4+ Series Reference Manual page 281

RM0432
Bits 31:10 Reserved, must be kept at reset value.
Bit 9 OSPI2RST: OctoSPI2 memory interface reset
Bit 8 OSPI1RST: OctoSPI1 memory interface reset
Bits 7:1 Reserved, must be kept at reset value.
Bit 0 FMCRST: Flexible memory controller reset
6.4.13 APB1 peripheral reset register 1 (RCC_APB1RSTR1)
Address offset: 0x38
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access
31 30 29
LPTIM1 OPAMP DAC1 PWRR
RST RST RST
rw rw rw
15 14 13
SPI3RS SPI2RS
Res. Res.
T T
rw rw
Bit 31 LPTIM1RST: Low Power Timer 1 reset
Bit 30 OPAMPRST: OPAMP interface reset
Bit 29 DAC1RST: DAC1 interface reset
Bit 28 PWRRST: Power interface reset
Set and cleared by software.
0: No effect
1: Reset OctoSPI2
Set and cleared by software.
0: No effect
1: Reset OctoSPI1
Set and cleared by software.
0: No effect
1: Reset FMC
28 27 26 25
CAN1R
Res. Res.
ST ST
rw rw
12 11 10 9
Res. Res. Res.
Set and cleared by software.
0: No effect
1: Reset LPTIM1
Set and cleared by software.
0: No effect
1: Reset OPAMP interface
Set and cleared by software.
0: No effect
1: Reset DAC1 interface
Set and cleared by software.
0: No effect
1: Reset PWR
24 23 22 21
CRSRS I2C3R I2C2R I2C1R
T ST ST ST
rw rw rw
8 7 6
TIM7R
Res. Res. Res.
ST
rw
RM0432 Rev 6
Reset and clock control (RCC)
20 19 18
UART5 UART4 USART3
RST RST RST
rw rw rw
5 4 3 2
TIM6R TIM5R TIM4RS
ST ST T
rw rw rw
17 16
USART2
Res.
RST
rw
1 0
TIM3RS TIM2R
T ST
rw rw
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