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DSI Host (DSIHOST) applied to STM32L4R9xx and STM32L4S9xx only
Bit 1 VSP: VSYNC Polarity
Bit 0 DEP: Data Enable Polarity
30.15.7
DSI Host Low-Power mode Configuration Register (DSI_LPMCR)
Address offset: 0x0018
Reset value: 0x0000 0000
31
30
29
28
Res.
Res.
Res.
Res.
15
14
13
12
Res.
Res.
Res.
Res.
Bits 31: 24 Reserved, must be kept at reset value
Bits 23: 16 LPSIZE: Largest Packet Size
Bits 15: 8 Reserved, must be kept at reset value
Bits 7: 0 VLPSIZE: VACT Largest Packet Size
30.15.8
DSI Host Protocol Configuration Register (DSI_PCR)
Address offset: 0x002C
Reset value: 0x0000 0000
31
30
29
28
Res.
Res.
Res.
Res.
15
14
13
12
Res.
Res.
Res.
Res.
988/2301
This bit configures the polarity of VSYNC pin.
0: Shutdown pin active high (default).
1: Shutdown pin active low.
This bit configures the polarity of Data Enable pin.
0: Data Enable pin active high (default).
1: Data Enable pin active low.
27
26
25
Res.
Res.
Res.
11
10
9
Res.
Res.
Res.
This field is used for the transmission of commands in Low-Power mode. It defines the
size, in bytes, of the largest packet that can fit in a line during VSA, VBP and VFP regions.
This field is used for the transmission of commands in Low-Power mode. It defines the
size, in bytes, of the largest packet that can fit in a line during VACT regions.
27
26
25
24
Res.
Res.
Res.
Res.
11
10
9
Res.
Res.
Res.
Res.
24
23
22
21
Res.
8
7
6
5
Res.
23
22
21
Res.
Res.
Res.
8
7
6
5
Res.
Res.
Res.
RM0432 Rev 6
20
19
18
LPSIZE[7:0]
rw
4
3
2
VLPSIZE[7:0]
20
19
18
Res.
Res.
Res.
4
3
2
CRCRXE ECCRXE
BTAE
rw
rw
rw
RM0432
17
16
1
0
17
16
Res.
Res.
1
0
ETRXE ETTXE
rw
rw
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