ST STM32L4+ Series Reference Manual page 963

RM0432
Special Sdd Control
An additional current path can be activated on both clock lane and data lane to meet the
Sdd parameter defined in the MIPI
TX
This activation is done setting the SDDC bit of the DSI_WPCR1 register.
Custom lane configuration
To ease DSI integration, lane pins can be swapped and/or High-Speed signal can be
inverted on a lane as described in
Invert High-Speed signal on lane
Custom timing configuration
Some of the MIPI
Table 207.
®
M
IPI timing
t
CLK-POST
t
LPX (Clock lane)
t
HS_EXIT
t
LPX (Data lane)
t
HS-ZERO
t
HS-TRAIL
t
HS-PREPARE
t
CLK-ZERO
t
CLK-PREPARE
All this values can be programmed only when the DSI is stopped (CR.DSIEN = 0 and
CR.EN = 0).
DSI Host (DSIHOST) applied to STM32L4R9xx and STM32L4S9xx only
Table 206. Custom lane configuration
Function
Swap lane pins
®
D-PHY timing can be tuned for specific purpose as described in
Table 207. Custom timing parameters
Enable bit in
DSI_WPCR0
TCLKPOSTEN
TLPXCEN
THSEXITEN
TLPXDEN
THSZEROEN
THSTRAIL
THSPREPEN
TCLKZEROEN
TCLKPREPEN
®
D-PHY Specification.
Table 206.
Lane
Clock lane
Data lane 0
Data lane 1
Clock lane
Data lane 0
Data lane 1
Configuration
register
DSI_WPCR4 TCLKPOST
DSI_WPCR3
THSZERO
THSTRAIL
THSPREP
DSI_WPCR2
TCLKZERO
TCLKPREP
RM0432 Rev 6
Enable bit in DSI_WPCR0
SWCL
SWDL0
SWDL1
HSICL
HSIDL0
HSIDL1
Default
Field
value
200
TLPXC 100
THSEXIT 200
TLPXD 100
175
140
126
195
120
Default
duration
100 ns + 120*UI
50 ns
100 ns + 40*UI
50 ns
175 ns + 8*UI
70 ns + 8*UI
63 ns + 12*UI
390 ns
60 ns + 20*UI
963/2301
1044