ST STM32L4+ Series Reference Manual page 107

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offering a continuous address space with the SRAM1 and SRAM3.

SRAM2 parity check

The user can enable the SRAM2 parity check using the option bit SRAM2_PE in the user

option byte (refer to

The data bus width is 36 bits because 4 bits are available for parity check (1 bit per byte) in

order to increase memory robustness, as required for instance by Class B or SIL norms.

The parity bits are computed and stored when writing into the SRAM2. Then, they are

automatically checked when reading. If one bit fails, an NMI is generated. The same error

can also be linked to the BRK_IN Break input of TIM1/TIM8/TIM15/TIM16/TIM17, with the

SPL control bit in the

Parity Error flag (SPF) is available in the

(SYSCFG_CFGR2).

When enabling the RAM parity check, it is advised to initialize by software the whole RAM

memory at the beginning of the code, to avoid getting parity errors when reading non-

initialized locations.

SRAM2 Write protection

The SRAM2 can be write protected with a page granularity of 1 Kbyte.

Section 3.4.1: Option bytes

SYSCFG configuration register 2

Table 3. SRAM2 organization

description).

SYSCFG configuration register 2

Start address

RM0432 Rev 6

(SYSCFG_CFGR2). The SRAM2

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