ST STM32L4+ Series Reference Manual page 510

Flexible static memory controller (FSMC)
Mode A - SRAM/FRAM/PSRAM (CRAM) OE toggling
A[25:0]
NBL[x:0]
NEx
NOE
NWE
Data bus
1. NBL[1:0] are driven low during the read access
A[25:0]
NBL[x:0]
NEx
NOE
NWE
Data bus
The differences compared with Mode 1 are the toggling of NOE and the independent read
and write timings.
510/2301
Figure 50. Mode A read access waveforms
High
NBLSET ADDSET HCLK cycles
HCLK
cycles
Figure 51. Mode A write access waveforms
NBLSET ADDSET HCLK cycles
HCLK
cycles
RM0432 Rev 6
Memory transaction
Data driven by memory
DATAST HCLK cycles
Memory transaction
Data driven by controller
DATAST HCLK cycles
RM0432
DATAHLD
HCLK cycles
MSv41681V1
DATAHLD +1
HCLK cycles
MSv41665V1