ST STM32L4+ Series Reference Manual page 320

Reset and clock control (RCC)
Off-
Register
set
RCC_
APB2SMENR
0x80
Reset value
RCC_CCIPR
0x88
Reset value
RCC_BDCR
0x90
Reset value
RCC_CSR
0x94
0 0 0 0 0 0 0 0 0
Reset value
RCC_CRRCR
0x98
Reset value
RCC_CCIPR2
0x9C
Reset value
RCC_DLYCF
GR
0xA4h
Reset value
Refer to
320/2301
Table 38. RCC register map and reset values (continued)
1 1 1
0 0 0 0
0 0
Section 2.2 on page 91
1 1 1 1 1
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0
x x x x x x x x x
0 0 0 0
for the register boundary addresses.
RM0432 Rev 6
1 1 1 1
RTC
SEL
[1:0]
0 0 0 0 0 0 0 0 0 0
MSIS
RANGE
[3:0]
0 1 1 0
HSI48CAL[8:0]
0 0 0 0 0 0 0 0 0 0 0 0 0
OCTOSPI
2_DLY
0 0 0 0 0 0 0 0
RM0432
1
LSE
DRV
[1:0]
0 0 0
0 0
OCTOSPI
1_DLY