ST STM32L4+ Series Reference Manual page 543

RM0432
18.8.2 NAND Flash supported memories and transactions
Table 116
allowed (or not supported) by the NAND Flash controller are shown in gray.
Device
NAND 8-bit
NAND 16-bit
18.8.3 Timing diagrams for NAND Flash memory
The NAND Flash memory bank is managed through a set of registers:
•
Control register: FMC_PCR
•
Interrupt status register: FMC_SR
•
ECC register: FMC_ECCR
•
Timing register for Common memory space: FMC_PMEM
•
Timing register for Attribute memory space: FMC_PATT
Each timing configuration register contains three parameters used to define number of
HCLK cycles for the three phases of any NAND Flash access, plus one parameter that
defines the timing for starting driving the data bus when a write access is performed.
Figure 66
that Attribute memory space access timings are similar.
shows the supported devices, access modes and transactions. Transactions not
Table 116. Supported memories and transactions
Mode R/W
Asynchronous R
Asynchronous W
Asynchronous R
Asynchronous W
Asynchronous R
Asynchronous W
Asynchronous R
Asynchronous W
Asynchronous R
Asynchronous W
Asynchronous R
Asynchronous W
shows the timing parameter definitions for common memory accesses, knowing
Flexible static memory controller (FSMC)
AHB Memory
data size data size not allowed
8 8
8 8
16 8
16 8
32 8
32 8
8 16
8 16
16 16
16 16
32 16
32 16
RM0432 Rev 6
Allowed/
Comments
Y
Y
Y Split into 2 FMC accesses
Y Split into 2 FMC accesses
Y Split into 4 FMC accesses
Y Split into 4 FMC accesses
Y
N
Y
Y
Y Split into 2 FMC accesses
Y Split into 2 FMC accesses
-
-
-
-
-
-
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